Z80189 Datasheet, PDF (87/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
Enhancement Detail
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
PC HOST Address Selection. There are a total of 4 regis-
ters addresses that are accessible by the PC HOST. They
are as follows:
Function
Address
HA9-HA2 programmable
HA1 HA0
Host Output Register 0
0
0
Host Output/Input Register 1
0
1
Host I/O Status Register
1
0
*Host Output to HDMAT1 Register 1
1
The HA9-HA2 is programmable by writing the contents into
Port A Data Register. The PC HOST access will occur
during a PC HOST input/output cycle at the programmed
address range (/HRD or /HWR=0, HAEN=0,
PA[9:2]=PADATA[7:0]). NOTE: PADATA SHOULD BE
WRITTEN WITH THE ADDRESS RANGE PRIOR TO
ENABLING THIS FEATURE.
* If the Host DMA Mailbox 1 function is disabled (bit 1 of
HMC register is zero), a Host write in the programmed
Mailbox range with HA1,0=1,1, will cause the host data to
be latched into the HDMAT1 register. This can be used as
an auxiliary host output register. Note that a host read from
this address is invalid.
765 43210
00000000
Figure 107. Host Output Register 0 (HOR0)
(180 MPU Read Only Address XXD3H)
(PC Host Read/Write HA9-2 (PADATA) + 00b)
765 43210
00000000
765 43210
000 00000
Unlock Bit
Host Output Register 0
Data Available
Host Output Register 1
Data Available
Host Input Register 1
Data Available
Auxilliary Bits
Host I/O Mailbox Enable
Figure 110. Host I/O Status Register (HIOS)
(180 MPU Read/Write Address xxD5H)
(PC Host Read Only HA9-HA2 (PADATA) + 10b)
Bit 7. Host I/O Mailbox Enable. The Z180 must write a logic
one to this bit to enable the Host I/O Mailbox. When this bit
is at zero (default), Host accesses are disabled. This bit is
only writable by the Z180, but is readable by both Z180 and
PC Host. When this bit is zero, registers D3, D4 and D5
cannot be read or written except for a write to the enable
bit in register D5 bit 7. Also, when this bit is zero the Host
side is not accessible. Once this bit is set, all registers
become visible to the Z180 and the Host.
Note: The PADATA should be programmed with HA9:HA2
address range prior to setting this bit. This bit should be
programmed as zero when the COM Decode Mux (CDR bit
0) is disabled.
Bits 6-4. Auxiliary bits. these bits can be written by the
Z180 and can be read by both the PC HOST and the Z180.
Note that the PC HOST cannot write to these bits. The
Auxillary Bits are zero by default and have no function other
than to serve as scratch bits for the HOST I/O Mailbox.
Figure 108. Host Output Register 1 (HOR1)
(180 MPU Read Only Address XXD4H)
(PC Host Write Only HA9-2 (PADATA) +01b)
765 43210
00000000
Figure 109. Host Input Register 1 (HIR1)
(180 MPU Write Only Address XXD4H)
(PC Host Read Only HA9-2 (PADATA) + 01b)
Bit 3. Host Input Register 1 Data Available. This bit be-
comes set when the Z180 writes to the Host Input Register
1. A PC Host read of the Host Input Register 1 will cause
this bit to clear. This bit cannot be set unless the Host I/O
Mailbox enable bit is set.
Bit 1. Host Output Register 0 Data Available. This bit
becomes set when the PC Host writes to the Host Output
Register 0. A Z180 read of the Host Output Register 0 will
cause this bit to clear. This bit cannot be set unless the Host
I/O Mailbox enable bit is set.
DS971890301
87