Z80189 Datasheet, PDF (80/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Interrupt Enable Register (Continued)
Bits 7,6,5,4 Reserved
These bits will always read 0 (PC and MPU)
Bit 6-Bit 0
These bits do not affect the Z80189 directly; however, they
can be read by the Z180 MPU and the 16550 MIMIC
modes can be emulated by the Z180 MPU.
Bit 3 Modem Status IRQ
If bits 0,1,2 or 3 of the Modem Status Register are set and
this enable bit is a logic 1, then an interrupt to the PC is
generated.
Bit 2 Receiver Line Status IRQ
If bits 1,2,3 or 4 of the LSR are set and this enable bit is a
logic 1, then an interrupt to the PC is generated.
Bit 1 Transmitter Holding Register Empty IRQ
If bit 5 of the LSR is set and this enable bit is a logic 1, then
an interrupt to the PC is generated.
Bit 0 Received Data Available IRQ
If bit 0 of the LSR is set or a Receiver Timeout occurs and
this enable bit is a logic 1, then an interrupt to the PC is
generated.
Line Control Register
Modem Control Register
7 65 4 321 0
0 00 0 0 00 0
DTS
RTS
Out 1
Out 2
Loop
Reserved
PC/XT/AT Read/Write, PC/XT/AT Address 4H
Z180 MPU Read Only, Z180 MU Address XXF4H
Figure 97. Modem Control Register
765 43210
0 00 0 0 00 0
Word Length Sel.
Number of Stop Bits
Parity Enable
Even Parity Sel.
Stick Parity
Set Break
DALB
PC/XT/AT Read/Write, PC/XT/AT Address 3H
Z180 MPU Read Only, Z180 MU Address XXF3H
Figure 96. Line Control Register
Bit 7 Divisor Latch Access Bit (DALB)
This bit allows access to the divisor latch by the PC/XT/AT.
If this bit is set to a one, access to the Transmitter, Receiver
and Interrupt Enable Registers is disabled, and when an
access is made to address 0, the Divisor Latch Least
Significant byte is accessed and if an access is made to
address 1, the Divisor Latch Most Significant byte is
accessed.
Bit 7-5 Reserved
Reserved for future use, always 0.
Bit 4 Loop
When this bit is set to a one then:
RI = Out 1
DCD = Out 2
DSR = DTR
CTS = RTS
Emulation of the loop back feature of the 16550 UART must
be done by the Z180 MPU except for the above conditions.
Bit 3 Out 2
This bit controls the state on the active HINTR pin if bits 2
and 1 of the MIMIC Master Control Register are a 10. Or
else it can be read by the Z180 MPU.
Bit 2-Bit 0
These bits have no direct control of the 16550 MIMIC
interface and the Z180 MPU must emulate the function if it
is to be implemented.
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DS971890301