Z80189 Datasheet, PDF (88/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
HOST INPUT/OUTPUT MAILBOX ENHANCEMENTS (Continued)
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Bit 0. Unlock Bit. When the Host I/O Mailbox is enabled, a
PC Host Write to Address 0FBHex will cause this bit to set.
A PC host write to address 0F9hex will cause this bit to
reset. The data written to these registers will NOT be
stored. A read access or access with HAEN=1 will NOT
cause this bit to toggle. Note that this bit has no function
other than a status bit (there is no locking or unlocking
caused by the state of this bit). The state of the unlock bit
is not controlled by the Host I/O Mailbox bit. Any I/O write
to FB will set the bit and a write to F9 will clear it regardless
of the state of the Host I/O Mailbox enable bit. Note that the
data written to 0FBhex or 0F9hex will not be stored by the
Z189.
If COM Port decode is disabled and COM Port decode
mux is enabled (default), COM Decode Pins HA9-HA3,
HAEN are ignored inputs. If HC1 is forced low the MIMIC
Data latch will be forced open. Therefore, care should be
taken that the HC1//HCS pin is NEVER connected directly
to logic high or low, when COM Port Decode is disabled.
/HCS pin can also be programmed as an output for debug
purposes. When the /HCS Force bit (Bit 7 in the COM Port
Decode Register) is enabled, the /HCS pin will be asserted
low whenever the MIMIC is being accessed by the PC host.
This feature is only available when the COM Port Decode
is enabled.
I/O Chip Select w/Prog. Range
The Z80187 has two I/O Chip Selects labelled
/IOCS1 and /IOCS2. The /IOCS1 will have same function-
ality as the Z80182’s /IOCS pin (multiplexed with IEO and
active during I/O accesses between ranges XX80H to
XXBFH). The IOCS pins will be asserted if /IORQ is active,
/M1 is inactive, and address compare is within range.
The Z80189 also has a secondary IOCS labeled
/IOCS2. This pin will be active for I/O accesses in the range
of XXC0H - XXC7H or XXC8H-XXCFH. The /IOCS2 pin will
be multiplexed over the E pin when enabled.
COM Port Decode
COM Port decode allows MIMIC to be selected when PC
address HA9-HA3 specifies a selected COM port address
range by HC pins 1 and 2 (selects COM Port address 1-4).
HC1 and HC2 can be read in software and program an
appropriate comport range for the decode circuitry. HC1
and HC2 can also be used for general input purposes. The
status of these pins can also be read when the COM
Decode Mux is disabled.
A dual HINTR option will provide two MIMIC Interrupt
requests to the HOST. HINTR1 will be asserted during a
MIMIC interrupt request when COM Decode is configured
for COM 1 & 3. HINTR2 will be asserted during a MIMIC
interrupt request when COM Decode is configured for
COM 2 & 4. The unasserted HINTR line will be tri-stated.
Note that during initialization, the COM Decode Regis-
ter must be written to before the System Configuration
Register.
Single Baud Rate Generator
A Baud Rate Generator is included to provide emulation
timing for the MIMIC device. This BRG is very similar to
ESCC BRG in functionality. There are 2x8 bit registers to
program the clock divider. The input to the BRG is the PHI
clock output of the S180 core.
The time constant required for a specific bit rate is as
follows:
Time constant (decimal) = (PHI freq. / (2*baud rate))-2
This formula is exactly the same as used in the ESCC.
The output of the BRG is directly connected to MIMIC
emulation counter input.
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DS971890301