Z80189 Datasheet, PDF (29/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
/HWR. Host Write (Input, active Low). In Z80189, this input
is used by the PC/XT/AT to signal the 16550 MIMIC
interface that a write operation is taking place.
/HRD. Host Read (Input, active Low). In Z80189, this input
is used by the PC/XT/AT to signal the 16550 MIMIC
interface that a read operation is taking place.
PC7-PC0. Parallel Port C (Input/Output). These lines can
be configured as inputs or outputs on a bit by bit basis for
bits PC5-PC0. Bits PC7 and PC6 are input only and read
the level of the external /INT2 and /INT1 pins. When /INT2
and/or /INT1 are in edge capture mode writing a ‘1’ to the
respective PC7, PC6 bit clears the interrupt capture latch.
Writing a ‘0’ has no effect.
HINTR1, HINTR2. Host Interrupt (Output, active High tri-
state). In Z80189, this output is used by the 16550 MIMIC
interface to signal the PC/XT/AT that an interrupt is pend-
ing. In Z80189 COM Port Decode mode, the MIMIC inter-
rupt request can be routed to either HINTR1 or 2 depend-
ing on the COM Port Decode selected. The deselected
HINTR line will be forced to tri-state, while the selected
HINTR will follow what is programmed in the MIMIC Master
Control Register.
HC1, HC2. Host COM Select Pin 1&2 (Input). HC1 and HC2
are general-purpose inputs that can be used for COM Port
selection. The status of these pins are read by use of the
CDR register. The status of these pins can be used by
firmware to select the appropriate COM Port address
decode range.
Emulation Signals
EV1, EV2. Emulation Select (Input). These two pins
determine the emulation mode the Z180 MPU is in. They
are as follows:
EV2 EV1
Mode 0 0 0 Normal mode, on-chip Z180 bus
master.
Mode 1 0 1 Emulation Adapter Mode
Mode 2 1 0 Emulator Probe Mode
Mode 3 1 1 Reserved
System Control Signals
PC DMA Mailbox Signals
/HDACK0, /HDACK1. Host DMA Acknowledge (Input,
active Low). This input signal indicates to the Z80189 that
the PC DMA controller has acknowledged the request and
will begin data transfer. /HDACK0 is multiplexed with
/CKA0 and /DREQ0. /HDACK1 is multiplexed with
/BUSREQ.
ST. Status (Output, active High). This signal is used with
the M1 and /HALT output to decode the status of the CPU
machine cycle.
/RESET. Reset Signal (Input, Active Low). /RESET signal
is used for initializing the MPU and other devices in the
system. It must be kept in the active state for a period of at
least 6 system clock cycles.
HDRQ0, HDRQ1. Host DMA Request (output, active high,
tri-state). This output requests to the PC DMA controller
that the Z80189 is ready for a DMA data transfer. HDRQ is
multiplexed with /RTS0. HDRQ1 is multiplexed with
/BUSACK.
Parallel Ports
PA7-PA0. Parallel Port A (Input/Output). These lines can
be configured as inputs or outputs on a bit-by-bit basis
when the Z80189 is operated in mode 0.
PB7-PB0. Parallel Port B (Input/Output). These lines can
be configured as inputs or outputs on a bit-by-bit basis
when the port function is selected in the System
Configuration register.
IEI. Interrupt Enable Signal (Input, active High). IEI is used
with the IEO to form a priority daisy chain when there is
more than one interrupt driven peripheral.
IE0. Interrupt Enable Output Signal (Output, active High).
In the daisy-chain interrupt control, IEO controls the interrupt
of external peripherals. IEO is active when IEI is “1” and the
CPU is not servicing an interrupt from the on-chip
peripherals. This pin is multiplexed with /IOCS1.
/IOCS1. I/O Chip Select 1 (output, active Low) is an
auxiliary chip select that decodes A7, A6, /IORQ, /M1 and
effectively decodes the address space XX80 to XXBF for
I/O transactions. A15 through A8 are not decoded so that
the chip select is active in all pages of I/O address space.
The /IOCS1 function is the default on power on or reset
condition and is changed by programming bit 2 in the
Interrupt Edge/Pin Mux Register.
DS971890301
29