Z80189 Datasheet, PDF (33/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189 MPU FUNCTIONAL DESCRIPTION
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
The Z80189 includes a Zilog Z8S180 MPU (Static Z80180
MPU). This allows software code compatibility with exist-
ing Z80/Z180 software code. The following is an overview
of the major functional units of the Z80189.
Architecture
The Z80189 combines a high performance CPU core with
a variety of system and I/O resources useful in a broad
range of applications. The CPU core consists of four
functional blocks:
s Clock Generator
s Bus State Controller (Dynamic Memory Refresh)
s Memory Management Unit (MMU)
s Central Processing Unit (CPU).
The integrated I/O resources make up the remaining
functional blocks:
s Direct Memory Access (DMA control—two channels)
s Asynchronous Serial Communications Controller
(ASCI, two channels)
s Programmable Reload Timers (PRT, two channels)
s Clocked Serial I/O
s 16550 Compatible MIMIC Interface
s COM Port Decoder
s PC DMA Mailbox Registers
s Host I/O Mailbox Registers
Clock Generator. This logic generates the system clock
from either an external crystal or clock input. The external
clock is divided by two, or one if programmed, and is
provided to both internal and external devices.
In addition, there is also a clock multiplier feature which
doubles the internal clock frequency from that of the
external clock input.
Bus State Controller. This logic performs all of the status
and bus control activity associated with both the CPU and
some on-chip peripherals. This includes wait state timing,
reset cycles, DRAM refresh, and DMA bus exchanges.
Interrupt Controller. This logic monitors and prioritizes
the variety of internal and external interrupts and traps to
provide the correct responses from the CPU. To maintain
compatibility with the Z80 CPU, three different interrupt
modes are supported.
Memory Management Unit. The MMU allows the user to
“map” the memory used by the CPU (logically only 64
Kbytes) into the 1 Mbyte addressing range supported by
the Z80189. The organization of the MMU object code
maintains compatibility with the Z80 CPU while offering
access to an extended memory space. This is accom-
plished by using an effective “common area-banked area”
scheme.
Central Processing Unit. The CPU is microcoded to
provide a core that is object-code compatible with the Z80
CPU. It also provides a superset of the Z80 instruction set,
including 8-bit multiply. This core has been modified to
allow many of the instructions to execute in fewer clock
cycles.
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