Z80189 Datasheet, PDF (39/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
/M1
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
If the M1E bit of the operation Mode Control Register is set
to 1, the RETI cycle occurs only once. The /M1 output is
asserted LOW during the opcode fetch cycle, the /INT0
acknowledge cycle, and the first machine cycle of the /NMI
acknowledge. When M1E bit is rest to 0, the /M1 output is
normally inactive an asserted LOW only during the refetch
of the RETI instruction sequence and during /INTO
acknowledge cycle.
Z8S180 POWER-DOWN MODES
The following is a detailed description of the enhance-
ments to the Z8S180 from the standard Z80180 in the areas
of STANDBY, IDLE, and STANDBY-QUICK RECOVERY
modes.
Add-On Features
There are five different power-down modes. SLEEP and
SYSTEM STOP are inherited from the Z80180. In SLEEP
mode, the CPU is in a stopped state while the on-chip
I/Os are still operating. In I/O STOP mode, the on-chip I/Os
are in a stopped state while leaving the CPU running. In
SYSTEM STOP mode, both the CPU and the on-chip I/Os
are in the stopped state to reduce current consumption.
The Z8S180 has added two additional power-down modes,
STANDBY and IDLE, to reduce current consumption even
further. The differences in these power-down modes are
summarized in Table 14.
Power-Down
Modes
SLEEP
I/O STOP
SYSTEM STOP
IDLE^†
STANDBY^†
CPU
Core
Stop
Running
Stop
Stop
Stop
On-Chip
I/O
Running
Stop
Stop
Stop
Stop
Table 14. Power Down Modes
OSC.
Running
Running
Running
Running
Stop
CLKOUT
Running
Running
Running
Stop
Stop
Recovery
Source
RESET, Interrupts
By Programming
RESET, Interrupts
RESET, Interrupts, BUSREQ
RESET, Interrupts, BUSREQ
Recovery Time
(Minimum)
1.5 Clock
-
1.5 Clock
8 +1.5 Clock
2¹⁷ +1.5 Clock (Normal Recovery)
2⁶ +1.5 Clock (Quick Recovery)
Notes:
† _{IDLE and STANDBY modes are only offered in the Z8S180. Note that the}
minimum recovery time can be achieved if INTERRUPT is used as the
Recovery Source.
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