Z80189 Datasheet, PDF (36/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189 MPU FUNCTIONAL DESCRIPTION (Continued)
DMA Controller
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
DMA Controller. The DMA controller provides high-speed
transfers between memory and I/O devices. Transfer op-
erations supported are memory-to-memory, memory to or
from I/O, and I/O-to-I/O. Transfer modes supported are
request, burst, and cycle steal. DMA transfers can access
the full 1 Mbyte addressing range with a block length up to
64 Kbytes, and can cross over the 64 Kbytes boundaries.
SM1-0
11
11
11
11
11
11
11
11
SAR18-16
000
001
010
011
100
101
110
111
Table 13. SAR18-16 and DAR18-16 I/O Device Encoding
Source
ext (CKA0/DREQ)
ASCI0 Rx
ASCI1 Rx
ext (/DREQ1)
*
*
*
*
DM1-0 DAR18-16
11
000
11
001
11
010
11
011
11
100
11
101
11
110
11
111
* Reserved do not use.
Destination
ext (CKA0//DREQ0)
ASCI0 Tx
ASCI1 Tx
ext (/DREQ1)
*
*
*
*
Asynchronous Serial Communications
Interface (ASCI)
The ASCI logic provides two individual full-duplex UARTs.
Each channel includes a programmable baud rate gen-
erator. The ASCI channels can also support a multiproces-
sor communications format. For ASCI0, up to three modem
control signals and one clock signal can be pinned out,
while ASCI1 has a data-only interface and 1 clock signal.
The receiver includes a 4-byte FIFO, plus a shift register as
shown in Figure 31.
Reset DCD (ASCI0 with Auto Enables) and
I/O Stop Mode Conditions
During Reset and in I/O Stop state, and for ASCI0 if /DCD0
is auto-enabled and is High, an ASCI is forced to the
following conditions:
s FIFO Empty
s All Error Bits Cleared (including those in the FIFO)
s Receive Enable Cleared (cntla bit 6 = 0)
s Transmit Enable Cleared (cntla bit 5 = 0).
If DCD is not auto-enabled, the /DCD pin has no effect on
the FIFOs or enable bits.
Overrun
Error
Error
Latches
4x4 Bit
Error
FIFO
PFOB
EERK
MP
Bit
4-Byte
Data FIFO
Notes:
PE = Parity Error
FE = Framing Error
OR = Overrun
BK = Break
MP = Multiprocessor Bit
Error
Shift Register
RXA
Figure 31. ASCI Receiver
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DS971890301