Z80189 Datasheet, PDF (98/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Z80189 ENHANCEMENTS REGISTER I(Z180 MPU ADDRESS D9H) (Continued)
7 65 4 321 0
0 0 0 X X XX0
PHI Output Disable
Reserved
Force Z180 Halt Mode
Forced /RAMCS
Memory Boundary
Forced /ROMCS
Memory Boundary
Figure 123. Z80189 Enhancements Register
(Z180 MPU Address 09H)
PARALLEL PORTS REGISTERS
The Z80189 has three eight bit bidirectional ports. Each bit
is individually programmable for input or output. The ports
consist of two registers: the Port Direction Control Register
and the Port Data Register. The port and direction register
can be accessed in any page of I/O space since only the
lowest eight address lines are decoded. Bits PC7 and PC6
are input only bits and have the special function of reading
the external value of the /INT2 AND /INT1 pins. Writing ‘1’
to these bits will clear the edge detect interrupt logic when
operating /INT2 and/or /INT1 in edge detect mode.
When Port B and Port C bits 5-0 are deselected in the
System Configuration Register, the Data and Data Direc-
tion Registers are still available as read/write scratch
registers. If a port is deselected and if the DDR bit is a ‘0’,
then the written value to that bit will be latched; and this
value can be read back. If a port is deselected and if the
DDR bit is a ‘1’, then you could read only the external pin
value; any write to that bit is latched but can be read back
only with DDR=0.
765 43210
1 11 1 1 11 1
PA Data Direction Register
0 = Output
1 = Input
Figure 124. PA Data Direction Register
(Z180 MPU Address XXEDH)
The data direction register determines which are inputs
and outputs in the PA Data Register. When a bit is set to a
one, the corresponding bit in the PA Data Register is an
input. If the bit is zero, then the corresponding bit is an
output.
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