Z80189 Datasheet, PDF (77/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Transmit Holding Register
When the PC/XT/AT writes to the Transmitter Holding
Register, the Z80189 responds by setting the appropriate
bit in the IP register and by generating an interrupt to the
Z180 MPU if it is enabled. When the Z180 MPU reads this
register, the Transmitter Holding register empty flag is set
(if the transmitter timer is enabled, this bit is set after the
timer times out). In FIFO mode of operation, this address is
used to read (Z180) and write (PC) the Transmitter FIFO.
Bit 6 and Bit 7 RCVR trigger LSB and MSB bits
This 2-bit field determines the number of required bytes in
the receiver FIFO before an interrupt to the PC occurs.
b7
b6
Trigger Level, Number of Bytes
0
0
01
0
1
04
1
0
08
1
1
14
7 65 4 321 0
X XX X XX XX
Transmitter Holding
Register
(PC Write Only, Address 00H, DLAB=0, R/W=Write)
(Z180 MPU Read Only, Address XXF0H)
Figure 90. Transmitter Holding Register
FIFO Control Register
7 65 4 321 0
0 00 0 0 00 0
FIFO Enable
RCVR FIFO Reset
XMIT FIFO Reset
Reserved (Must be 0)
Reserved
(Tx Overrun, MPU Only)
Reserved
(FCR Write, MPU Only)
RCVR Trigger (LSB)
RCVR Trigger (MSB)
PC/XT/AT Write Only, PC Address 02h
Z180 MPU Read Only, MPU Address XXE9H
Bit 4 and Bit 5 Reserved
Note: From the MPU side, bit 4 and bit 5 flag two sources
of interrupts. Bit 5 is a FIFO interrupt, indicating that the
FCR had changed; bit 4 is a Tx overrun interrupt, indicating
transmit overrun. A read of the FCR from the MPU side will
clear a previously set bit 4 or bit 5.
Bit 3 Reserved
Reserved for future use.
Bit 2 XMIT FIFO Reset
Setting this bit to a 1 will cause the transmitter FIFO pointer
logic to be reset; any data in the FIFO will be lost. This bit
is self clearing; however, a shadow bit exists that is cleared
only when read by the Z180 MPU, allowing the MPU to
monitor a FIFO reset by the PC.
Bit 1 RCVR FIFO Reset
Setting this bit to a 1 will cause the receiver FIFO pointer
logic to be reset; any data in the FIFO will be lost. This bit
is self clearing; however, a shadow bit exists that is cleared
only when read by the Z180 MPU, allowing the MPU to
monitor a FIFO reset by the PC.
Bit 0 FIFO Enable
The PC writes this bit to logic 1 to put the 16550 MIMIC into
FIFO mode. This bit must be a 1 when writing to the other
bits in this register or they will not be programmed. When
this bit changes state, any data in the FIFO’s or transmitter
holding and receiver buffer registers is lost and any pend-
ing interrupts are cleared.
Figure 91. FIFO Control Register
DS971890301
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