Z80189 Datasheet, PDF (83/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
PC MAILBOX DATA REGISTERS
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
HDMAT0 Host DMA Transmit Register 0,
Z180 Read Only, PC Write Only
HDMAT1 Host DMA Transmit Register 1,
Z180 Read Only, PC Write Only
3. Z189 hardware forces HDRQ inactive low on the
leading (falling) edge of /HWR during the /HDACK
cycle. Note that the HDREQ register bit is not to be
cleared yet, since the DMA cycle has not yet com-
pleted.
HDMAR0 Host DMA Receive Register 0,
Z180 Write Only, PC Read Only
4. The PC places valid data on the ISA bus (HD[0:7] and
asserts /HWR low.
HDMAR1 Host DMA Receive Register 1,
Z180 Write Only, PC Read Only
There are four separate 8-bit mailbox registers available
for DMA data. The I/O address for the mailbox registers will
be XXDOH for Mailbox 0 and XXD1H for Mailbox 1. Note
that there are separate registers for read and write access.
The mailbox register can latch data from the host data bus
HD[0:7] and is readable by the Z180 using IN0 a, (DOH) or
IN0 a, (D1H). Data can be written into the mailbox registers
using the OUT0 (DOH), a or OUT0 (D1H), a and can output
its contents onto HD [0:7} during a PC HOST DMA access.
Note: The following is a description of other Z189 signals
relevant in a PC DMA Mailbox access.
– The /HDDIS signal will go low during a PC DMA Read
access (selected /HDACK and /HRD going low).
– The /HCS pin will not asserted low during a PC DMA
Mailbox access (/HDACK active) if the HDRQ/HDACK
channel is enabled.
5. Z189 hardware latches data into the HDMAT register
on the trailing (rising) edge of /HWR while /HDACK is
still active low. On this same edge, hardware clears the
HDREQ register bit.
6. Z180 software polls the HDREQ bit until it's 0, and then
can input the data byte from HDMAT. The polling of the
HDREQ bit is used to indicate when the PC DMA Write
has been completed. The PC software program should
program its DMA controller to stop DMA at the end of
valid data or when commanded by the application.
When the Z180 software sets HDREQ, but doesn't see
the HDREQ bit automatically cleared within a reason-
able time (because /HDACK remains inactive high),
then software can stop the PC DMA write by resetting
the HDREQ bit.
7. Messages on the COM Port confirm that the PC DMA
write operation is complete. Z180 software clears
HDREQ, then clears HDMAE to disable host DMA.
PC DMA Read
PC DMA Write
Through commands exchanged over the MIMIC COM
Port, PC software and the Z180 agree to configure DMA for
a PC DMA write, in which data flows from PC memory to,
for example, a modem's speaker codec. The PC sets up its
8237 DMA controller in auto-initialize mode to assure that
data is always available whenever the modem makes a
DMA request. The Z180 clears HDREQ and sets HDMAE,
forcing HDRQ low.
The PC DMA Write proceeds as follows:
PC DMA Read is almost the same as a PC DMA Write, but
the data flows the other direction through the HDMAR
register.
Through commands exchanged over the MIMIC COM
Port, PC software and the Z180 agree to configure DMA for
a PC DMA Read, in which data flows from, for example, a
modem's microphone codec to PC memory. The PC sets
up its 8237 DMA controller in auto-initialize mode to assure
that there is always buffer space available whenever the
modem makes a DMA request. The Z180 clears HDREQ
and sets HDMAE, forcing HDRQ low.
1. Z180 software writes a 1 to the HDREQ bit, causing the
HDRQ pin to go active High.
2. The rising edge of HDRQ causes the 8237 DMA
controller to begin a memory-read, I/O-write DMA bus
cycle on the ISA bus at the end of the current PC bus
cycle. The PC asserts /HDACK low to acknowledge
the DMA request.
The PC DMA Read proceeds as follows:
1. Z180 software outputs the data byte to HDMAR, where
it is latched.
2. Z180 software writes a 1 to the HDREQ bit, causing the
HDRQ pin to go active high.
DS971890301
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