Z80189 Datasheet, PDF (18/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
AC CHARACTERISTICS (Continued)
Read/Write External Bus Master Timing
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Table 1. External Bus Master Timing
No Sym
Parameter
Z8L189-20 MHz Z80189-33 MHz
Min
Max Min
Max Unit
1 TsA(wf)(rf) Address to WR or RD Fall Time
20
20
ns
2 TsIO(wf)(rf) IORQ Fall to WR or RD Fall Time
20
20
ns
3 Th
Data Hold Time (from WR Rise)
0
0
ns
4 TdRD(DO) RD Fall to Data Out Delay
35
35
ns
5 TdRIr(DOz) RD, IORQ Rise to Data Float Time
0
0
ns
6 TsDI(WRf) Data In to WR Fall Setup Time
20
20
ns
7 TsA(IORQf) Address to IORQ Fall Setup Time
35
35
ns
8 TsA(RDf)
Address to RD Fall Setup Time
35
35
ns
9 TsA(WRf) Address to WR Fall Setup Time
35
35
ns
Notes
No Sym
1 TsAR
2 TsCSR
3 TsAW
4 TsCSW
5 tAh
6 tCSh
7 tDs
8 tDh
9 tWc
10 tRvD
11 tHz
12 tRc
13 tRDD
14 tSINT
15 tRINT
16 tHR
17 TSTI
18 TIR
Table 2. 16550 MIMIC Timing
Parameter
Z8L189-20 MHz Z80189-33 MHz
Min
Max Min
Max
Address Setup to HRD Fall Time
30
30
Address Setup to CS Fall Time
30
30
Address Setup to HWR Fall Time
30
30
HCS Setup to HWR Fall Time
30
30
Address Hold Time
20
20
HCS Hold Time
20
20
Data Setup Time
Data Hold Time
Write Cycle Delay
30
30
30
30
2.5
2.5
Delay from HRD Fall to Data Valid
HRD Rise to Data Float Delay
Read Cycle Delay
125
125
100
100
125
125
HRD Toggle to Driver Enable/Disable
60
60
Delay fromwr RBR Reg. to Assert HINTR
2.0
2.0
Delay from /HRD of RBR to Deassert HINTR
2.0
2.0
Delay from /WR THR to Reset HINTR
2.5
2.5
Delay from MPU /RD of THR to Assert HINTR
2.0
2.0
Delay from /RD to Reset Interrupt
75
75
Unit Notes
ns
ns
ns
ns
ns
ns
ns
ns
phi cycles
ns
ns
ns
ns
phi cycles
phi cycles
phi cycles
phi cycles
ns
18
DS971890301