Z80189 Datasheet, PDF (89/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
Baud Rate Generator Register
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
The following registers are used to store BRG constant.
The timer is enabled after setting bit 0 of IOBRG register.
Design is such that on-the-fly modification of registers do
not cause irregular BRG output.
7 65 4 321 0
1 1 1 1 11 1 1
Lower Byte of
Time Constant
765 43210
1 1 11 11 1 1
Upper Byte of
Time Constant
Figure 112. BRGH Baud Rate Generator High
(Address XXE9H) Default 00 Hex
Figure 111. BRGL Baud Rate Generator Low
(Address XXE0H) Default 00 Hex
IOBRG Register
The following register handles the IOCS feature and MIMIC
BRG. IOBRG-IOCS & BRG enable (Address XXD6H)
Default 04 hex.
7 65 4 321 0
0 00 0 0 10 0
BRG Enable
/IOCS2 Range
1 = I/O Access between
xxC0h-xxC7
0 = I/O Access between
xxC8h-xxCF
/IOCS2 Enable
/INTO Assertion of
MIMIC Access
Reserved as 0
Figure 113. IOBRG-IOCS and BRG Enable
(Address XXD6H)
Bits 4-7 Reserved
Bit 3
R/W
/INT0 assertion on MIMIC access. When this bit
is enabled, and the /HALT is active (power-down)
any HOST access to the MIMIC will cause a low
edge. Since this interrupt source has no vector,
/INT0 MODE 1 must be used when enabling this
mode. This is disabled on power-up. /INT0 asser-
tion is released when /HALT is deasserted.
Note: The THRE bit is forced to 0 on the PC side to prevent
THR overrun during powerdown modes when this feature
is enabled. When the MIMIC comes out of power-down,
THRE resumes normal functionality.
Bit 2
/IOCS2 enable
When set, IOCS2 is muxed over E pin. This is
enabled on reset.
Bit 1
R/W
/IOCS2 range.
When set, IOCS2 is active during I/O accesses
between XXC0H-XXC7H.
When reset, IOCS2 is active during I/O accesses
between XXC8H-XXCFH. This is disabled on
power-up.
Bit 0
R/W
BRG enable. When set,
the MIMIC BRG begins counting down to gener-
ate a programmed square wave to the MIMIC
emulation timers. This is disabled on power-up.
Note: When waking from Standby Mode using a PC-THR
write, the THRE bit will not reset until clock is stabilized.
This may cause a THR overrun. Therefore, data integrity
cannot be guaranteed. Care should be taken so that
standby mode is only used when data integrity is not
essential.
DS971890301
89