Z80189 Datasheet, PDF (75/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Bit 0 Force 16450 mode (Write/Read)
(Reset value=0) This bit=1 will force the MIMIC into 16450
mode. Bit 0 in the FCR reg is forced to zero as well as the
MIMIC internal FIFO enable. Bits 7 and 6 in the IIR will
remain at their last value when this bit is set.
765 43210
1 11 1 1 11 1
Transmitter Timeout
Constant
7 65 4 321 0
11 1 11 1 11
Figure 86. Transmitter Time-out Timer Constant
(Z180 MPU Add XXEBH)
Rec Timeout Constant
Figure 85. Receiver Time-out Timer Constant
(Z180 MPU Add XXEAH)
This register contains an 8-bit constant for emulation of the
16550 4 character time-out feature. Software must deter-
mine the value to load into this register based on the bit rate
and word length specified by the MIMIC interface with the
PC. This timer receives its input from the BRG Clock. This
timer is enabled to down count when the enable bit in the
FSCR register is set and the trigger level has not been
reached on the RCVR FIFO. The counter will reload each
time there is a read or write to the RCVR FIFO.
This register contains an 8-bit constant for determining the
interval for the transmitter time-out timer. If allowed to
decrement to zero, this timer will interrupt the MPU by
setting the THR bit in the IUS/IP register. This timer re-
ceives its input from the BRG Clock. The timer is enabled
to down count when the enable bit in the FSCR register is
set and the trigger level has not been reached on the XMIT
FIFO. The counter will reload each time there is a read or
write to the XMIT FIFO.
TRANSMIT AND RECEIVE TIMERS
Because of the speed at which data transfers can take
place between the Z180 MPU and the PC/XT/AT, two
timers have been added to alleviate any software prob-
lems that a high-speed data transfer might cause. These
timers allow the programmer to slow down the data trans-
fer just as if the 16550 MIMIC interface had to shift the data
in and out. The Timers receive their input from the BRG
Clock. This allows the programmer access to a 24-bit timer
to slow down the data transfer.
7 65 4 321 0
1 11 1 11 11
Transmitter Time
Constant
Figure 87. Transmitter Time Constant Register
(Z180 MPU Address XXFAH)
When a write from the PC/XT/AT is made to the Transmitter
Holding register, an interrupt to the Z180 MPU is gener-
ated. The Z180 MPU then reads the data in the Transmitter
Holding Register. Upon this read if the Transmitter timer is
enabled, the time constant from the Transmitter Time
Constant Register is loaded into the Transmitter timer and
enables the count. After the timer reaches a count of zero,
the Transmitter Holding Register Empty bit is set. However,
the above is only true when the PC/XT/AT is reading the
Transmitter Holding Register Empty bit. To allow the Z180
MPU to know that it has already read the byte of data, a
mirrored Transmitter Holding Register Empty bit is set
immediately following a read from the Transmitter Holding
Register. This mirrored bit is always read back to the Z180
MPU when it reads the Line Status Register. If the transmit-
ter timer is not enabled when the Z180 MPU reads the
transmitter holding register, then both Transmitter Holding
Register Empty bits are set immediately. In FIFO mode of
operation, the effect is similar in that the status to PC is
always delayed such that a PC interrupt for empty FIFO will
not occur before the time required for each character read
from the FIFO by the Z180 has elapsed. The effect is that
the PC will not see data requests from an empty FIFO any
faster than would occur with a true UART when the delay
feature is enabled. This timer is also used to delay data
transfer from THR Register to Z80189 TSR buffer in double
buffer mode.
DS971890301
75