Z80189 Datasheet, PDF(74/107 Page) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

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Z80189 Datasheet, PDF (74/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

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Zilog

PRELIMINARY

Interrupt Vector Register (Continued)

Z80189/Z8L189

GENERAL-PURPOSE EMBEDDED CONTROLLERS

Bit 0 Opcode (Read/Write)

This bit is always a zero when the VIS bit is a one. If the VIS

bit is a zero, then this bit reads back what was last written

to it.

This register serves both interrupt modes. When the VIS bit

is a zero, the last value written to the register can be read

back. If the VIS bit is a one and an interrupt is pending, the

value read will be the last value written to the upper nibble

plus the status for the interrupt that is pending. If no

interrupt is pending, then the last value written to the upper

nibble plus the lower nibble will be read from the register.

If the vector includes the status, then the lower four bits of

the vector will change asynchronously depending on the

interrupting source. Since this vector changes asynchro-

nously, then the interrupt service routine to read the IVEC

INTACK cycle if that IRQ does not have its IUS set.

7 65 4 321 0

0 00 0 0 00 0

FORCE_450

Receive Timeout to PC Host Enable

TEMT_DBLBUFF

Reserved (Always 0)

XMIT Timeout Enable

RCVR Timeout Enable

XMIT Trigger (LSB)

XMIT Trigger (MSB)

Figure 84. FIFO Status and Control Register

(Z180 MPU Read/Write Add XXECH)

Bit 7 and Bit 6 XMIT Trigger MSB, LSB

This field determines the number of bytes available to read

in the transmitter FIFO before an interrupt will occur to the

MPU:

Bit 5 Receiver Time-out Enable

This bit enables the Z80189 Receiver Time-out Timer that

is used to emulate the four character time-out delay that is

specified by the 16550. An RTO interrupt will occur under

the following conditions: no read or write to the RCVR FIFO,

data bytes are available, but below the PC trigger level, or

the receiver timeout timer reaches zero.

Bit 4 Transmitter Time-out Enable

This bit enables the Z80189 timer that is used to interrupt

the Z180 MPU if characters are available, but are below the

trigger level. The timer is enabled to count down if this bit

is one and the number of bytes is below the set transmitter

trigger level. The timer will time-out and interrupt the MPU

if no read or write to the XMIT FIFO takes place within the

timer interval.

Bit 3 Reserved for Future Use

Always write and read as â0â by users. Writing â1â enables

a test mode for emulation timers.

Bit 2 Double Buffer Mode (Write/Read)

(Reset value=0) Setting this bit will enable (only in 16450

mode) the TEMT hardware emulation and transmitter double

buffering.

Double Buffer

This enables a transmit shift register (TSR) to act as a slave

The Z180 reads from the transmit shift register. This allows

the PC to write two consecutive bytes into the MIMIC.

TEMT Emulation

If character delay emulation is being used, the TEMT is set

as follows:

The TSR is emptied and the associated delay logic has set

the (delayed) THRE bit in the LSR.

At this time a one character delay timer begins. After this

timer reaches zero count, the TEMT bit will be set if the THR

and TSR output buffer are empty. TEMT is clear whenever

there is data in either THR or the TSR output buffer.

Level (#bytes)

Bit 1 Receive Timeout to the PC Host (Write/Read)

(Reset Value=0) setting this bit will enable the RTO timeout

to emulate the 16550 device. If enabled, the RTO timer will

not start timeout until all delayed characters have been

clocked through the receiver character delay emulation

logic. This will prevent an RTO from occurring before a

(delayed) receiver trigger level interrupt. When cleared,

the RTO will begin timeout from the last read or write to the

receiver FIFO.

DS971890301

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