Z80189 Datasheet, PDF (7/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
TIMING DIAGRAMS
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Opcode Fetch Cycle
T1
T2
TW
T3
5
4
2
3
ø
1
6
Address
/WAIT
20
20
19
19
7
12
/MREQ
8
/IORQ
/RD
9
/WR
/M1
14
10
18
I/O Write Cycle †
I/O Read Cycle †
T1
T2
TW
T3
11
7
29
11
13
28
13
9
22
25
26 and 26a
T1
11
11
ST
Data
IN
Data
OUT
62
/RESET
68
17
63
67
15
16
23
15
24
62
67
16
21
27
63
68
Figure 5. CPU Timing
(Opcode Fetch Cycle, Memory Read/Write Cycle I/O Read/Write Cycle)
DS971890301
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