Z80189 Datasheet, PDF (78/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
MIMIC Modification Register
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Interrupt Identification Register
D7 D6 D5 D4 D3 D2 D1 D0
0 00 0 0 00 0
Reserved - Program to Zero
16550/450 RCVR Overrun
Figure 92. MIMIC Modification Register
(Z189 MPU Write only, Address XXE9H)
Bit 7-2 Reserved. Program to zero.
Bit 1 RCVR Overrun Modification
The actual 16450/16550 device allows the last position in
FIFO to be overwritten by MPU during receiver overrun
condition. When this bit is enabled (programmed to 1) the
last position in FIFO can be overwritten by Z180 during
receiver overrun. This feature is disabled by default. When
this modification is not enabled, the MIMIC will ignore any
write to RBR during an overrun condition.
Bit 0 Reserved
Program to zero.
765 43210
00000000
0 if Interrupt Pending
Interrupt ID Bit (0)
Interrupt ID Bit (1)
Interrupt ID Bit (2)
Always 0
FIFO Enabled Flag
PC/XT/AT Read Only, PC Address 02H
Z180 MPU No Access
Figure 93. Interrupt Identification Register
Bit 7 and Bit 6 FIFO’s enabled
These bits will read 1 if FIFO mode is enabled on the
MIMIC.
Bit 5 and Bit 4 Always read 0
Reserved bits.
Bits 3-1 Interrupt ID bits
This 3 bit field is used to determine the highest priority
interrupt pending. See Table 16 for the 3-bit field
descriptions.
Table 16. Interrupt Identification Field
b3
b2
b1
Priority
Interrupt Source
Inter. Reset Control
0
1
1
Highest
Overrun, Parity,
Framing error or
Break detect bits
set by MPU.
Read Line Stat. Reg.
0
1
0
2nd
Received Data
trigger level
RCVR FIFO drops below
trigger level.
1
1
0
2nd
Receiver Time-out
with data in
RCVR FIFO.
Read RCVR FIFO.
0
0
1
3rd
Transmitter
Holding Register
Empty.
Writing to the
IIR or transmitter
Holding Register.
0
0
0
4th
MODEM status:
CTS,DSR,RI or
DCD.
Reading the MODEM
78
DS971890301