Z80189 Datasheet, PDF (68/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
16550 MIMIC FIFO DESCRIPTION (Continued)
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Table 15. 16550 Line Status Register
Error
Description
How to Set
Error in
RCVR
FIFO
At least one data byte available
in FIFO with one error
At least one error in receiver
FIFO
*TEMT
Transmitter empty
MPU writes a 1
† *THRE
Transmitter holding
register is empty
When MPU has
read or emptied
the holding register
Break
Detect
Break occurs when
received data input
is held in logic-0
for longer than a
full word transmission
MPU writes 1
Framing
Error
Received character
did not have a valid
stop bit
MPU writes 1
Parity
Error
Received character
did not have correct
even or odd parity
MPU writes 1
Overrun
Error
Overlapping received
characters, thereby
destroying the
previous character
MPU makes
two writes
to receiver
buffer register
†Data
Ready
Indicates complete
incoming data has
been received
Notes:
* The TEMT and THRE bits take on different functions when
TEMT/Double Buffer mode is enabled.
† These signals are delayed to HOST when using character
emulation delay.
MPU writes to
RCVR FIFO or
receiver buffer
register
How to Clear
When there are no more
errors
MPU writes a 0
When holding register
is not empty
There is a
PC-side read
of the LSR
There is a
PC-side read
of the LSR
There is a
PC-side read
of the LSR
There is a
PC-side read
of the LSR
Empty Receiver
or Receiver FIFO
68
DS971890301