Z80189 Datasheet, PDF (38/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189 MPU FUNCTIONAL DESCRIPTION (Continued)
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Baud Rate Generator
The Baud Rate Generator (BRG) has two modes. The first
is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a
16-bit time constant register, and is identical to the ESCC
BRG. This allows a common baud rate of up to 512 Kbps
to be selected. The BRG can also be disabled in favor of
an external clock on the CKA pin.
The Receiver and Transmitter will subsequently divide the
output of the BRG (or the signal from the CKA pin) by 1, 16
or 64, under the control of the DR bit in the CNTLB register,
and the X1 bit in the ASCI Extension Control Register. To
compute baud rate, use the following formulas.
If ss2,1,0 = 111, baud rate = f / Clock mode
CKA
else if BRG mode baud rate = f / (2 * (TC+2) * Clock
PHI
mode)
else baud rate = f / ((10 + 20*PS) * 2^ss * Clock mode)
PHI
Where:
BRG mode is bit 3 of the ASEXT register
PS is bit 5 of the CNTLB register
TC is the 16-bit value in the ASCI Time Constant registers
The TC value for a given baud rate is:
TC = (f_PHI / (2 * baud rate * Clock mode)) - 2
Clock mode depends on bit 4 in ASEXT and bit 3 in CNTLB:
X1 DR
Clock Mode
0
0 = 16
0
1 = 64
1
0 =1
1
1 = Reserved, do not use.
The requirement of having very close to the 50% duty cycle
when the CKA pin is used as an input, has been removed
on the 189. Minimum High and Low times on CKA0 are
typical of most CMOS devices.
RDRF is set, and if enabled an Rx Interrupt or DMA
Request is generated, when the receiver transfers a char-
acter from the Rx Shift Register to the Rx FIFO. The FIFO
merely provides margin against overruns. When there’s
more than one character in the FIFO, and software or a
DMA channel reads a character, RDRF either remains set
or is cleared and then immediately set again. Similarly, if a
receive interrupt service routine doesn’t read all the char-
acters in the RxFIFO, RDRF and the interrupt request
remain asserted.
The Rx DMA request is disabled when any of the error flags
PE or FE or OVRN are set, so that software can identify with
which character the problem is associated.
Programmable Reload Timer (PRT)
This logic consists of two separate channels, each con-
taining a 16-bit counter (timer) and count reload register.
The time base for the counters is derived from the system
clock (divided by 20) before reaching the counter. PRT
channel 1 provides an optional output to allow for wave-
form generation.
The T output of PRT1 is available on a multiplexed pin.
OUT
Clocked Serial I/O (CSIO)
The CSI0 channel provides a half-duplex serial transmitter
and receiver. This channel can be used for simple high-
speed data connection to another microprocessor or
microcomputer.
2^ss depends on the three LS bits of the CNTLB register:
ss2 ss1 ss0
2^ss
0
0
0 =1
0
0
1 =2
0
1
0 =4
0
1
1 =8
1
0
0 = 16
1
0
1 = 32
1
1
0 = 64
1
1
1 = External Clock from CKA0
(see above).
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