Z80189 Datasheet, PDF (71/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
16550 MIMIC INTERFACE REGISTERS
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
The 16550 MIMIC interface is controlled by the MMC
register. Setting it allows for different modes of operation
such as using the eight bit counters and which IRQ
structure is used with the PC/XT/AT.
7 65 4 321 0
0 00 0 0 00 0
VIS Vector Include Status
0 = Mode 0 Interrupts
1 = Mode 2 Interrupts
HINTR1
00 = Normal
01 = Wire And
10 = Out 2 Control
11 = Reserved
Reserved as 0
Reserved as 0
Reserved as 0
Rx Timer Enable
Tx Timer Enable
Figure 80. MIMIC Master Control Register
(Z180 MPU Address XXFFH)
Bit 7 Transmit Timer Delay Counter
Enable (Read/Write)
If bit 7 is set to a one, it enables the transmit delay timer.
When the Z180 reads the Transmit Register, the transmit
delay timer is automatically loaded with the Transmit Time
Constant Register and the timer is enabled to countdown
to zero. This timer delays setting the Transmitter Holding
Register Empty (THRE) bit until the timer times out. If this
bit is zero, then THRE is set immediately on a Z180 read of
the Transmit Register.
Both counters are single pass and stop on a count of zero.
Their purpose is to delay data transfer just as if the 16550
UART had to shift the data in and out. This is provided to
alleviate any software problems a high speed continuous
data transfer might cause to existing software. If this is not
a problem, then data can be read and written as fast as the
two machines can access the devices. In FIFO mode of
operation, the timers are used to delay the status to the PC
interface by the time that would be required to actually shift
the characters out or in if an actual UART were present.
Bit 5 Reserved as 0
Bit 4 Reserved as 0
Bit 3 Reserved as 0
Bit 2,1 Interrupt Select (Read/Write)
Bits 2, 1
00 If both bits 2 and 1 are set to zero, then the active
HINTR1 pin is set to normal 16550 MIMIC mode.
01 If bit 2 is zero and bit 1 is one, then the 16550
MIMIC will enable a wire AND condition on the
active HINTR1 pin to the PC/XT/AT.
10 If bit 2 is one and bit 1 is zero, then the active
HINTR1 pin will be driven only if out 2 of the
Modem Control register is a one. If out 2 is a zero,
then the active HINTR1 pin will be tri-stated.
11 Both bits should never be set to one. This is a
reserved condition and should not be used.
Bit 0 Vector Include Status (Read/Write)
This bit is used to select the interrupt response mode of the
Z180. A 0 in this bit enables mode 0 interrupts; a 1 enables
mode 2 response.
Bit 6 Receive Timer Delay Counter
Enable (Read/Write)
If bit 6 is set to a one, it enables the receive delay timer.
When the Z180 writes to the Receive Buffer, it loads the
receive delay timer from the Receive Time Constant Reg-
ister and enables the timer to countdown to zero. This timer
delays setting the Data Ready (DR) bit in the LSR until the
timer times out. If this bit is a zero, then DR is set immedi-
ately on a Z180 write to the Receive Buffer.
DS971890301
71