Z80189 Datasheet, PDF (16/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
AC CHARACTERISTICS (Continued)
(3V3_CCM=Hz5VCh±_{a1r0a%cteorrisVtCicCs=A3p.p3Vly}
± 10%, over specified temperature
Only to 5V Operation.)
range
unless
otherwise
noted
No Sym
41 tRFD1
42 tRFD2
43 tHAD1
44 tHAD2
45 tDRQS
46 tDRQH
47 tTED1
48 tTED2
49 tED1
50 tED2
51 PWEH
52 PWEL
53 tEr
54 tEf
55 tTOD
56 tSTDI
57 tSTDE
58 tSRSI
59 tSRHI
60 tSRSE
61 tSRHE
62 tRES
63 tREH
64 tOSC
65 tEXr
66 tEXf
67 tRr
68 tRf
69 tIr
70 tIf
71 tdCS
Parameter
Z8L189-20 MHz Z80189-33 MHz
Min
Max Min
Max
Unit Notes
/PHI to /RFSH Delay
/PHI to /RFSH Delay
/PHI to /HALT Delay
/PHI to /HALT Delay
20
15
ns
20
15
ns
15
15
ns
15
15
ns
DREQ Setup Time to /PHI
DREQ Hold Time from /PHI
/PHI to /TEND Delay
/PHI to /TEND Delay
/PHI to /E Delay
20
15
ns
20
15
ns
25
15
ns
25
15
ns
30
15
ns
/PHI /or to /E Delay
E Pulse Width (High)
E Pulse Width (Low)
Enable Rise Time
Enable Fall Time
30
15
ns
25
20
ns
50
40
ns
10
10
ns
10
10
ns
/PHI to Timer Output Delay
CSI/O Transmit Data Delay (Internal Clock Operation)
CSI/O Transmit Data Delay (External Clock Operation)
CSI/O Receive Data Setup Time (Internal Clock Operation)
CSI/O Receive Data Hold Time (Internal Clock Operation)
75
75
7.5 tcyc+75
1
1
50
ns
60
ns
7.5 tcyc+60 ns
1
phi cycles
1
phi cycles
CSI/O Receive Data Setup Time (External Clock Operation)
CSI/O Receive Data Hold Time (External Clock Operation)
RESET Setup Time to /PHI
40
RESET Hold Time from /PHI
25
Oscillator Stabilization Time
1
1
25
15
20
1
phi cycles
1
phi cycles
ns
ns
20
ns
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
Reset Rise Time
Reset Fall Time
Input Rise Time (Except EXTAL, RESET)
Input Fall Time (Except EXTAL, RESET)
MREQ Valid to RAMCS and ROMCS Valid Delay
10
5
ns
10
5
ns
50
50
ms [2]
50
50
ms [2]
50
50
ns [2]
50
50
ns [2]
5
5
ns [3]
Notes:
[1] tcyc = tCHW + tCLW + tcf + tcr.
[2] If the rise and fall times are greater than the specified maximums,
other specifications will not be met.
[3] SL1832 is test screened such that specifications 8, 15, and 71 are
tested to 18 ns (Tmeol + Tors + Trlcs = 18 ns).
16
DS971890301