Z80189 Datasheet, PDF (82/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PC DMA Mailbox
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
General Description
The concept behind the PC DMA Mailbox Registers is to
provide a path for the PC DMA data transfer separate from
the MIMIC COM Port. Commands and data flow over the
COM Port, while the DMA path is reserved for other
purposes. The PC DMA Mailbox Register functionality will
require control registers which will allow PC DMA data
transfer between the PC memory and for example, a
modem speaker/microphone codec. Note that the transfer
will be driven by the PC Host DMAs. This feature only
allows for the handshaking and data path for the PC Host
DMAs.
The host (PC) DMA channels will use the following four
Z189 pins for the PC DMA Mailbox feature. Each pair of
pins are individually selectable:
HDRQ0
Host DMA request 0, Z189 output,
active high, high-Z control
/HDACK0 Host DMA acknowledge 0, Z189 input,
active low
HDRQ1 Host DMA request 1, Z189 output,
active high, high-z control
/HDACK1 Host DMA acknowledge 1, Z189 input,
active low
The pins labeled as HDRQ0 and HDRQ1 are asserted by
the Z180 to signal the PC HOST of a DMA request. The pins
labelled /HDACK0 and /HDACK1 are asserted by the PC
to signal a PC DMA access. Dual request/acknowledge
pairs are provided to interface with two PC DMA channels.
The PC Mailbox channels are independent and can be
used simultaneously or individually for jumperless DMA
channel selection.
PC DMA MAILBOX BIT FUNCTIONS
HDREQ. Host DMA request bit, default value = 0
Two bits will serve to request a PC HOST DMA access.
When this bit is set and the Host DMA channel is enabled
(HDMAE=1), the corresponding HDRQ pin will be as-
serted high. Z180 software sets this bit (OUT0 instruction)
to request a DMA transfer, and Z189 hardware clears the
bit when the byte transfer is complete. Z180 software can
also clear the bit. The Z180 will be able to read the bit (IN0
instruction) to indicate that the transfer has occurred.
I/O address of XXD2h (HMC register) contains a request
bit for each DMA channel (bit 4 and bit 5 of the HMC
register). Write enable bits are provided to simplify code
(read-modify-write cycles not required).
HDMAE Host DMA enable default=0, HDRQ is tri-stated
Two bits will serve to enable the dual DMA channels
request/acknowledge pairs. When the HDMAE1 bit is set,
the output will become fully driven, otherwise (HDMAE1 bit
is reset) the HDRQ1 will be tri-stated. When the HDMAE0
bit is set the HDRQ0 output will become fully driven,
otherwise, the HDRQ0 output will be tri-stated.
I/O address XXD2h is assigned the HMC register. Bits 0
and 1 of the HMC register are respectively assigned
HDMAE0 and HDMAE1.
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