Z80189 Datasheet, PDF (81/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Modem Status Register
Scratch Register
7 65 4 321 0
0 00 0 0 00 0
DCTS
DDSR
TERI
DDCD
CTS
DSR
RI
DCD
PC/XT/AT Read Only, PC/XT/AT Address 6H
Z180 MPU Read/Write Bits 7-4, Z180 MPU Address XXF6H
7 65 4 321 0
X XX X XX X X
Scratch Register
PC/XT/AT Read/Write, PC/XT/AT Address 07H
Z180 MPU Read Only, Z180 MPU Address XXF7H
Figure 99. Scratch Register
Bits 7-0 Scratch Register
This register is used by the PC/XT/AT programmer for
temporary data storage. The Z180 MPU is able to read this
register. If the PC/XT/AT writes to this register, no interrupt
to the Z180 MPU is generated.
Figure 98. Modem Status Register
Bit 7 Data Carrier Detect
This bit must be written by the Z180 MPU.
Bit 6 Ring Indicator
This bit must be written by the Z180 MPU.
Divisor Latch (LS)
7 65 4 321 0
X XX X XX X X
Divisor Latch (LS)
PC/XT/AT Read/Write, PC/XT/AT Address 00H and DLAB = 1
Z180 MPU Read Only, Z180 MPU Address XXF8H
Bit 5 Data Set Ready
This bit must be written by the Z180 MPU.
Figure 100. Divisor Latch (LS)
Bit 4 Clear to Send
This bit must be written by the Z180 MPU.
Bit 3 Delta Data Carrier Detect
This bit is set to a one whenever the Data Carrier Detect bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Bit 7-0 Divisor Latch Most Significant (MS)
This register contains the low order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up the application.
Divisor Latch (MS)
Bit 2 Trailing Edge Ring Indicator
This bit is set to a one on the falling edge of the Ring
Indicator bit. This bit is reset when the PC/XT/AT reads the
Modem Status Register.
Bit 1 Delta Data Set Ready
This bit is set to a one whenever the Data Set Ready bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
Bit 0 Delta Clear To Send
This bit is set to a one whenever the Clear To Send bit
changes state. This bit is reset when the PC/XT/AT reads
the Modem Status Register.
765 43210
X XX X XX X X
Divisor Latch (MS)
PC/XT/AT Read/Write, PC/XT/AT Address 01H and DLAB = 1
Z180 MPU Read Only, Z180 MPU Address XXF9H
Figure 101. Divisor Latch (MS)
Bit 7-0 Divisor Latch Most Significant (MS)
This register contains the high order byte of the Baud rate
divisor. Writing to this register with the PC/XT/AT will
generate an interrupt to the Z180 MPU. It can then read the
Baud rate divisor and set up application.
DS971890301
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