Z80189 Datasheet, PDF (28/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PIN DESCRIPTION (Continued)
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
/RFSH. Refresh (Output, active Low, tri-state). Together
with /MREQ,/RFSH indicates that the current CPU machine
cycle and the contents of the address bus should be used
for refresh of dynamic memories. The low order 8 bits of the
address bus (A7-A0) contain the refresh address.
/MRD. Memory Read (Output, active Low, tri-state). /MRD
is active when both the internal /MREQ and /RD signals are
active.
/MWR. Memory write (output, active Low, tri-state). /MWR
is active when both the internal /MREQ and /WR signals are
active.
Z180^™ MPU UART and SIO Signals
CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional,
active High). When in output mode, these pins are
the transmit and receive clock outputs from the ASCI
baud rate generators. When in input mode, these pins
serve as the external clock inputs for the ASCI baud rate
generators.
CKS. Serial Clock (Bidirectional, active High). This line is
the clock for the CSIO channel.
/DCD0. Data Carrier Detect 0 (Input, active Low). This is a
programmable modem control signal for ASCI channel 0.
/RTS0. Request to Send 0 (Output, active Low, tri-state).
This is a programmable modem control signal for ASCI
channel 0.
/CTS0/CTS1. Clear to Send 0 (Input, active Low). This line
is a modem control signal for the ASCI channel 0 and 1.
TXA0. Transmit Data 0 (Output, active High). This signal is
the transmitted data from the ASCI channel 0.
TXS. Clocked Serial Transmit Data (Output, active High).
This line is the transmitted data from the CSIO channel.
RXA0. Receive Data 0 (Input, active High). This signal is
the receive data to ASCI channel 0.
RXS. Clocked Serial Receive Data (Input, active High).
This line is the receiver data for the CSIO channel.
RXA1. Received Data ASCI Channel 1.
TXA1. Transmitted Data ASCI Channel 1.
Z180^™ MPU DMA Signals
/TEND0. Transfer End 0 (outputs, active Low). This output
is asserted active during the last write cycle of a DMA
operation. It is used to indicate the end of the block
transfer.
/DREQ0, /DREQ1. DMA request 0 and 1 (Input, active
Low). /DREQ is used to request a DMA transfer from one
of the on-chip DMA channels. The DMA channels monitor
these inputs to determine when an external device is ready
for a read or write operation. These inputs can be pro-
grammed to be either level or edge sensed.
Z180^™ MPU Timer Signals
T . Timer Out (Output, active High). T is the pulse
OUT
OUT
output from PRT channel 1. This line is multiplexed with
HINTR1 of the 16550 MIMIC.
16550 MIMIC Interface Signals
HD7-HD0. Host Data Bus (Input/Output, tri-state). In
Z80189, the host data bus is used to communicate be-
tween the 16550 MIMIC interface and the PC/XT/AT. It is
multiplexed with the PA7-PA0 of parallel port A.
/HDDIS. Host Driver Disable (Output, active Low). In
Z80189, this signal goes low whenever the PC/XT/AT is
reading data from the 16550 MIMIC interface. The /HDDIS
pin should also go active low on each PC DMA read cycle.
HA2-HA0. Host Address (Input). In Z80189, these pins are
the address inputs to the 16550 MIMIC interface. This
address determines which register the PC/XT/AT accesses.
HA9-HA3, HAEN. Host COM Port Decode Address (In-
put). In Z80189, these pins are multiplexed when COM
Port Decode is enabled (default). These pins are used to
provide internal MIMIC Enable when HA9-HA3 match the
programmed MIMIC address field. HAEN is also used to
access the PC DMA Mailbox registers.
/HCS. Host Chip Select (Input, active Low). In Z80189, this
input is used by the PC/XT/AT to select the 16550 MIMIC
interface for an access. The /HCS input is disabled when
using the internal COM Port Decoder. When setting the
/HCS Force bit in the CDR register, the /HCS output is
asserted when HA3-HA9 is within the boundaries pro-
grammed by bits 3-4 of the CDR register and /HRD or
/HWR is asserted. /HCS is NOT asserted for PC DMA
Mailbox accesses.
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DS971890301