Z80189 Datasheet, PDF (85/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
PC MAILBOX DATA REGISTERS (Continued)
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
765 43210
11 0 0 00 00
0 = HDRQ0 Tri-State
1 = HDMA Enable
0 = HDRQ1 Tri-State
1 = HDMA Enable
HDRQ /HDACK0,
CKA0//DREQ0, /RTS0
0 = HDRQ0, /HDACK0 Select
1 = /RTS0, CKA0//DREQ0 Select
HDRQ1, /HDACK1,
/BUSACK, /BUSREQ
0 = HDRQ1, /HDACK1 Select
1 = /BUSACK, /BUSREQ Select
HDREQ0 (DMA request 0)
HDREQ1 (DMA request 1)
Revision Data Avail
Write Enable HDREQ0
Revision Data Avail
Write Enable HDREQ1
Figure 102. Host DMA Mailbox
Control Register, HMC
(Z180 MPU Read/Write Address XXD2H)
Bits 7 Write Enable HDREQ1 (Write only)
Revision Data Available (Read only)
Set this bit whenever setting/resetting the HDREQ1 bit.
When this bit is written with 1, bit 5 will be written into the
HDREQ bit and bits 0-3 are ignored. When this bit is written
with zero, bits 0-3 can be written and bit 5 is ignored. Note
that this bit does not change the write access to bits 4 and
6. The Write Enable is not latched and must be set for each
HDREQ1 write.
When bit 7 is read it is set upon powerup and becomes
reset during the 1st read of the HDMAT1 register.
Bits 6 Write Enable HDREQ0 (Write only)
Set this bit whenever setting/resetting the HDREQ0 bit.
When this bit is written with 1, bit 4 will be written into the
HDREQ0 bit and bits 0-3 are ignored. When this bit is
written with zero, bits 0-3 can be written and bit 4 is
ignored. Note that this bit does not change the write
access to bits 5 and 7. The Write enable is not latched and
must be set for each HDREQ0 write.
When bit 6 is read, it indicates the availability of the revision
data in the Host DMA transmit register (HDMAT0). When
the revision data is read by the Z180 CPU, this bit will
become reset and the revision data will no longer be
available in the HDMAT0 register.
Bit 5 HDREQ1 Bit
When Mailbox 1 is multiplexed and enabled (HDMAE1=1),
setting this bit will cause the HDRQ1 pin to go active high,
which puts out a request to the PC for a DMA transfer. Z189
hardware clears this bit when byte transfer is complete.
This bit is disabled upon reset. This bit can also be reset to
force the HDRQ1 pin to inactive low. Note that Bit 7 must
be set to modify HDREQ1.
Bit 4 HDREQ0 Bit
When Mailbox 0 is multiplexed and enabled (HDMAE0=1),
setting this bit will cause the HDRQ0 pin to go active high,
which puts out a request to the PC for a DMA transfer. Z189
hardware clears this bit when byte transfer is complete.
This bit is disabled upon reset. This bit can also be reset to
force the HDRQ0 pin to inactive low. Note that Bit 6 must
be set to modify HDREQ0.
Bit 3 HDRQ1/HDACK1, /BUSACK /BUSREQ
This bit selects the multiplexing that will occur between the
HDRQ1//BUSACK and the /HDACK1/BUSREQ pins. If this
bit is set to 0, the HDRQ1 and /HDACK1 functions are
enabled for this pin. Otherwise, if this bit is set to 1, the
/BUSACK and /BUSREQ functions are enabled for this pin.
This bit is reset to 0.
Bit 2 HDRQ/HDACK0, /RTS0 CKA0//DREQ0
This bit selects the multiplexing that will occur between the
HDRQ0//RTS0 and the /HDACK/CKA0//DREQ0 pins. If this
bit is set to 0, the HDRQ and /HDACK0 functions are
enabled for this pin. Otherwise, if this bit is set to 1, the
CKA0//DREQ0 and /RTS0 functions are enabled for this
pin. This bit is reset to 0.
Bit 1 HDMAE1 bit
When this bit is set to 1, it allows Mailbox 1 to request a PC
DMA cycle given that the Mailbox 1 pins are multiplexed
(bit 4=1). When this bit is cleared to 0, the HDREQ1 is tri-
stated if Mailbox 1 pins are multiplexed. When this bit is
cleared, the HDMAT1 can be used to store HOST OUTPUT
MAILBOX DATA.
Bit 0 HDMAE0 bit
When this bit is set to 1, it allows Mailbox 0 to request a PC
DMA cycle given that the Mailbox 0 pins are multiplexed
(bit 4=1). When this bit is cleared to 0, the HDREQ0 is tri-
stated if Mailbox 0 pins are multiplexed.
DS971890301
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