Z80189 Datasheet, PDF(90/107 Page) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

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Z80189 Datasheet, PDF (90/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

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Zilog

PRELIMINARY

HOST INPUT/OUTPUT MAILBOX ENHANCEMENTS (Continued)

Z80189/Z8L189

GENERAL-PURPOSE EMBEDDED CONTROLLERS

The register that handles and enables COM port decode

and multiplexing is as follows:

7 65 4 321 0

0 00 0 0 00 1

COM Port Decode MUX

State of HC1 (Read Only)

State of HC2

COM Port Decode Selection

Bit 4 3

COM 1 (3F8-3FF) Default

COM 2 (2F8-2FF)

COM 3 (3E8-3EF)

COM 4 (2E8-2EF)

COM Port Decode Enable

Dual HINTR

Reserved as 0

Figure 114. CDR - COM Decode Register

(Address XXD7H)

CDR - COM Decode Register (Address XXD7H) default

01hex

Bit 0

R/W

COM Port Decode Mux. When set, COM Port

Decode pins (HA9-HA3, HAEN HC1-2) are

enabled. This is set on default. Refer to multi-

plexing section for further detail.

Bit <1-2> Read only registers that specify the state of

HC1 and HC2 input pins when COM Port

select feature is enabled in bit 0.

Bit 1 represents HC1 input. Bit 2 represents

HC2 input. Since HC1 is multiplexed with

/HCS, care should be taken that if COM Port

Decode is disabled, /HCS is not forced low.

Bit <3-4> COM Port decode selection. These two bits

are used to select COM Port decode 1-4 as

R/W

follows:

Bit 5

R/W

Bit 6

R/W

Bit 7

decoder during a PC-DMA cycle. This circuitry is

not used when COM Port Decode (bit 5) is dis-

abled.

HA2-HA0 are used to select between internal

MIMIC registers.

COM Port Decode enable. When this bit

is set, HA3-HA9 inputs are used for COM Port

Decoder. The MIMIC will be accessible given

that the address inputs HA3-HA9 are within the

range programmed by bits 3 & 4 when HAEN

is active low.

Please refer to MULTIPLEXING section for de-

tails on pin HA3-HA9 muxing. This is disabled

on reset. When disabled, the COM Port De-

code inputs are still treated as inputs, but have

no affect on MIMIC operation.

Dual HINTR. When this bit is set, the

HINTR2 output will be asserted for MIMIC

interrupt requests when configured for COM 2

& 4. HINTR1 output will be asserted for MIMIC

interrupt requests when configured for COM 1

& 3. When disabled, HINTR2 is always inactive

(tri-stated) while HINTR1 is active for all MIMIC

interrupt requests. This is disabled on reset

(HINTR2 is tri-state on power-up).

Note that the unselected HINTR line will be tri-

stated while the active HINTR line will be driven

as per the MIMIC Master Control Register

/HCS Force Bit. When Bit 0 and Bit 5 of this

Logic Enabled), it forces the /HCS signal to be

exported out of the /HCS/HC1 pin. /HCS output

is asserted when HA3-HA9 is within the bound-

aries programmed by bits 3-4 of CDR (regard-

less of /HRD and /HWR). /HCS is NOT asserted

for PC DMA Mailbox accesses. If this bit is zero

(default), the /HCS/HC1 pin becomes an input.

Bit 4

Bit 3

COM 1 (3F8-3FF) default

COM 2 (2F8-2FF)

COM 3 (3E8-3EF)

COM 4 (2E8-2EF)

Note: The /HCS/HC1 pin is tied to both /HCS function and

HC1 functions simultaneously when bit 7 is reset to zero.

Therefore, MIMIC access is disabled until the first System

Configuration Register Write on COM Decode (bit 5) is

enabled. This mechanism prevents accidental bus con-

tention if /HCS/HC1 pin is pulled low.

MIMIC access will only be allowed if inputs HA9-

HA3 reflect the above address ranges and HAEN

is deasserted. HAEN is used to disable the COM

Note: The COM Decode Register must be written first,

prior to the System Configuration Register during initializa-

tion.

DS971890301

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