Z80189 Datasheet, PDF (15/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
AC CHARACTERISTICS
(3V3_CCM=Hz5VCh±_{a1r0a%cteorrisVtCicCs=A3p.p3Vly}
± 10%, over specified temperature
Only to 5V Operation.)
range
unless
otherwise
noted
No Sym
1
tcyc
2
tCHW
3
tCLW
4
tcf
5
tcr
6
tAD
7
tAS
8
tMED1
9
tRDD1
10 tM1D1
11 tAH
12 tMED2
13 tRDD2
14 tM1D2
15 tDRS
16 tDRH
17 tSTD1
18 tSTD2
19 tWS
20 tWH
21 tWDZ
22 tWRD1
23 tWDD
24 tWDS
25 tWRD2
26 tWRP
26a tWRP
27 tWDH
28 tIOD
29 tIOD2
30 tIOD3
31 tINTS
32 tINTH
33 tNMIW
34 tBRS
35 tBRH
36 tBAD1
37 tBAD2
38 tBZD
39 tMEWH
40 tMEWL
Parameter
Z8L189-20 MHz
Min
Max
Clock Cycle Time
Clock H Pulse Width
Clock L Pulse Width
Clock Fall Time
50
2000
15
15
10
Clock Rise Time
/PHI to Address Valid
Address Valid to /MREQ, /IRQ
/PHI to /MREQ Delay
/PHI to /RD Delay (IOC=1)
/ PHI to /RD Delay (IOC=0)
10
15
5
3
25
25
/PHI to /M1 Delay
35
Address Hold Time from (MREQ, IOREQ, RD, WR) 5
/PHI to /MREQ Delay
25
/PHI to /RD Delay
25
/PHI to /M1 Delay
40
Data Read Setup Time
Data Read Hold Time
/PHI to /ST Delay
/PHI to /ST Delay
WAIT Setup Time to /PHI
10
0
30
30
15
WAIT Hold Time from /PHI
/PHI to Data Float Display
/PHI to /WR Delay
/PHI to Write Data Delay Time
Write Data Setup Time to /WR
10
35
25
25
10
/PHI to /WR Delay
Write Pulse Width (Memory Write Cycle)
Write Pulse Width (I/O Write Cycle)
Write Data Hold Time from /WR
/PHI to /IORQ Delay (IOC=1)
/PHI to /IORQ Delay (IOC=0)
/PHI to /IORQ Delay
25
75
130
10
25
25
25
/M1 to /IORQ Delay
100
/INT Setup Time to /PHI
20
/INT Hold Time from /PHI
10
NMI Pulse Width
35
BUSREQ Setup Time to /PHI
10
BUSREQ Hold Time from /PHI
/PHI to /BUSACK Delay
/PHI to /BUSACK Delay
/PHI to Bus Floating Delay Time
MREQ Pulse Width (High)
MREQ Pulse Width (Low)
10
25
25
40
35
35
Z80189-33 MHz
Min
Max
33
2000
10
10
5
5
15
5
3
15
15
15
5
15
15
15
10
0
15
15
10
5
20
15
15
10
15
45
70
5
15
15
15
80
15
10
25
10
10
15
15
30
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
[1]
[1]
[1]
[1]
[1]
[3]
[3]
[2]
DS971890301
15