Z80189 Datasheet, PDF (52/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
FREE RUNNING COUNTER
PRELIMINARY
FRC
Read Only
Addr 18H
76543210
Figure 56. Free Running Counter
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
CPU CONTROL REGISTER
The Z8S180 has an additional register which allows the
programmer to select options that directly affect the CPU
performance as well as controlling the STANDBY operat-
ing mode of the chip. The CPU Control Register (CCR)
allows the programmer to change the divide-by-two inter-
nal clock to divide-by-one. In addition, applications where
EMI noise is a problem, the Z8S180 can reduce the output
drivers on selected groups of pins to 33% of normal pad
driver capability which minimizes the EMI noise generated
by the part.
CPU Control Register (CCR) Addr 1FH
D7 D6 D5 D4 D3 D2 D1 D0
0 000 00 00
Clock Divide
0 = XTAL/2
1 = XTAL/1
Standby/Idle Enable
00 = No Standby
01 = Idle After Sleep
10 = Standby After Sleep
11 = StandbyAfter Sleep
64 Cycle Exit
(Quick Recovery)
BREXT
0 = Ignore BUSREQ
In Standby/Idle
1 = Standby/Idle Exit
on BUSREQ
LNAD/DATA
0 = Standard Drive
1 = 33% Drive On
A19-A0, D7-D0
LNCPUCTL
0 = Standard Drive
1 = 33% Drive On CPU
Control Signals
LNIO
0 = Standard Drive
1 = 33% Drive or
ASCI Signals
LNPHI
0 = Standard Drive
1 = 33% Drive On
EXT.PHI Clock
Figure 57. CPU Control Register
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DS971890301