Z80189 Datasheet, PDF (96/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
INTERRUPT EDGE/PIN MUX REGISTERS
765 43210
00001100
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Halt Recovery Select
1 = 16 Cycle Delay on Halt Recovery
0 = No Wait Delay on Halt Recovery
Low Noise Select
1 = Select Low Noise for Z189 (not Z180)
0 = Select Normal Drive for Z189 Pins
IEO, /IOCS1 Select
1 = Select /IOCS1 Function
0 = Select IEO Function
/MREQ, /HRD,PC2, /MWR Select
1 Select /MRD, /MWR
0 Select /MREQ, PC2
/INT1 Mode Select
0X = Normal Level Detect
10 = Falling (Neg) Edge Det
11 = Rising (Pos) Edge Det
/INT2 Mode Select
0X = Normal Level Detect
10 = Falling (Neg) Edge Det
11 = Rising (Pos) Edge Det
Figure 122. Interrupt Edge/Pin Mux Register
(Z180 MPU Address XXDFH)
Bits 7-6 control the interrupt capture logic for the external
/INT2 PIN. When programmed as ‘0X’, the /INT2 pin per-
forms as the normal level detecting interrupt pin. When
programmed as ‘10’, the negative edge detection is en-
abled. Any falling edge will latch an active low on the
internal /INT2 of the Z180. This interrupt must be cleared by
writing a ‘1’ to bit 7 of the Port C Data Register. Program-
ming these control bits to ‘11’ will enable rising edge
interrupts to be latched. The latch is cleared in the same
fashion as the falling edge. Interrupt Capture logic is not
available in EV mode 1 (emulation adapter mode).
Bits 5-4 control the interrupt capture logic for the external
/INT1 PIN. When programmed as ‘0X’, the /INT1 pin per-
forms as the normal level detecting interrupt pin. When
programmed as ‘10’, the negative edge detection is en-
abled. Any falling edge will latch an active low on the
internal /INT1 of the Z180. This interrupt must be cleared by
writing a ‘1’ to bit 6 of the Port C Data Register. Program-
ming these control bits to ‘11’ will enable rising edge
interrupts to be latched. The latch is cleared in the same
fashion as the falling edge. Interrupt Capture Logic is not
available in EV mode 1 (emulator adaption mode).
Bit 3 Programming this bit to 1 selects the /MRD and the
/MWR outputs. When this bit is set, /MREQ will be removed
for the qualification of both /RAMCS and /ROMCS. By
programming this bit to 0, the /MREQ Z180 and PC2
outputs are enabled. This bit is 0 upon reset.
Bit 2 selects the /IOCS1 function which is the default for
power up and /RESET conditions. By programming this bit
to ‘0’, the IEO function is enabled for this multiplexed pin.
Bit 1 selects the low noise or normal drive feature for the
Z189 pins. The default at power up is normal drive for Z189
pins. By programming this bit to ‘1’, low noise for the Z189
pins is chosen (not the Z180 pins). Programming this bit to
‘0’ selects normal drive for the Z189 pins. Z189 pins
include: all MIMIC output pins, ROM/RAM chip selects, bit
I/O, IOCS1, IOCS2, and PC DMA Mailbox outputs.
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