Z80189 Datasheet, PDF (8/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
Ø
32
31
/INTI
33
/NMI
C7
/INTSCC
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
/M1 [1]
30
/IORQ [1]
16
15
/Data IN [1]
39
/MREQ [2]
41
40
42
/RFSH [2]
35
34
35
34
/BUSREQ
36
37
/BUSACK
38
38
Address
Data /MREQ,
/RD, /WR,
/IORQ
43
[3]
44
/HALT
Notes:
[1] During /INT0 acknowledge cycle [3] Output buffer is off at this point
[2] During refresh cycle
Figure 6. CPU Timing
(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)
8
DS971890301