Z80189 Datasheet, PDF (79/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
Bit 0 Interrupt Pending
This bit is logic 0 and interrupt is pending. When the PC
accesses the IIR, the contents of the register and all
pending interrupts are frozen. Any new interrupts will be
recorded, but not acknowledged during the IIR access.
Line Status Register
7 65 4 321 0
0 00 1 0 00 0
Data Ready
Overrun Error
Parity Error
Framing Error
Break Interrupt (BI)
THRE
TEMT
Error in RCVR FIFO
PC/XT/AT Read Only, PC Address 05H
Z180 MPU Read/Write Bits 6,4,3,2 MPU Address XXF5H
Figure 94. Line Status Register
Bit 7 Error in RCVR FIFO
In 16450 mode, this bit will read logic 0. In 16550 mode, this
bit is set if at least one data byte is available in the FIFO with
one of its associated error bits set. This bit will clear when
there are no more errors (or break detects) in the FIFO.
Bit 6 Transmitter Empty
This bit must be set or reset by the MPU by a write to this
register bit. If Double Buffer Mode is enabled this bit is set
automatically by hardware whenever both THR buffer and
TSR is empty.
Bit 5 Transmitter Holding Register Empty, THRE
This bit is set to one when either the THR has been read
(emptied) by the MPU (16450 mode) or the XMIT FIFO is
empty (16550 mode). This bit is set to 0 when either the
THR or XMIT FIFO become non-empty. A shadow bit exists
so that the register bit setting to 1 is delayed by the
Transmitter Timer if enabled. The MPU when reading this
bit will not see the delay. Both shadow and register bits are
cleared when the PC writes to the THR of XMIT FIFO.
Note: The THRE bit is forced to 0 in the PC side to prevent
THR overruns when /HALT is asserted (Powerdown Mode)
and bit 3 (/INTO assertion on MIMIC access feature) is set.
When the MIMIC comes out of powerdown (/HALT
deasserted), the THRE bit resumes normal functionality.
Bit 2, 3, 4 Parity Error, Framing Error, Break Detect
These bits are written, indirectly, by the MPU as follows:
The bits are first written to shadow bit locations when the
MPU write accesses the LSR. When the next character is
written to the Receiver Buffer or RCVR FIFO, the data in the
shadow bits is then copied to the LSR (16450 mode) or
FIFO RAM (16550 mode). In FIFO mode, the bits become
available to the PC when the data byte associated with the
bits is next to be read (top of FIFO). In FIFO mode, with
successive reads of the receiver, the status bits will be set
if an error occurs on any byte. Once the MPU writes to the
Receiver Buffer or RCVR FIFO, the shadow bits are auto
cleared. The register bits are cleared upon the PC reading
the LSR. In FIFO mode, these bits will be set if any byte has
the respective error bit set while the PC reads multiple
characters from the FIFO.
Bit 1 Overrun Error
This bit is set if the Z180 MPU makes two writes to the
Receiver Buffer before the PC reads the data in the Buffer
(16450 mode) or with a full RCVR FIFO (16550) mode. No
data will be transferred to the RCVR FIFO under these
circumstances. This bit is reset when the PC reads the Line
Status Register.
Bit 0 Data Ready
This bit is set to 1 when received data is available, either in
the RCVR FIFO (16550 mode) or Receiver Buffer Register
(16450 mode). This bit is set immediately upon the MPU
writing data to the Receiver Buffer or FIFO if the Receiver
Timer is not enabled but is delayed by the timer interval if
the Receiver Timer is enabled. For MPU read access, a
shadow bit exists, so that the MPU does not see the delay
the PC does. Both bits are cleared to logic zero immedi-
ately upon reading all the data in either the Receiver Buffer
or FIFO.
Interrupt Enable Register
7 65 4 321 0
0 00 0 0 00 0
Bit 0 Received Data Available Int.
Bit 1 THRE Interrupt
Bit 2 Receiver Line Status Int.
Bit 3 Modem Status Interrupt
Bit 7,6,5,4 always 0
PC/XT/AT Read/Write, PC Address 01H
Z180 MPU Read Only, Z180 MPU Address XXF1H
Figure 95. Interrupt Enable Register
DS971890301
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