Z80189 Datasheet, PDF (46/107 Pages) Zilog, Inc. – GENERAL-PURPOSE EMBEDDED CONTROLLERS

Zilog
PRELIMINARY
ASCI CHANNELS CONTROL REGISTERS (Continued)
STAT0
Addr 04H
Bit RDRF OVRN PE ^{FE RIE} /DCD0 TDRE TIE
Upon Reset
0
0
0
0
0
† †† 0
R/W ^{R R R R R/W R R R/W}
Z80189/Z8L189
GENERAL-PURPOSE EMBEDDED CONTROLLERS
† /DCD0 - Depending on the condition of /DCD0 Pin.
†† _{TDRE is reset to 0, when /CTSO input is high.}
/CTS0 Pin = L: TDRE = 1
/CTS0 Pin = H: TDRE = 0
Transmit Interrupt Enable
Transmit Data Register
Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
Figure 36. ASCI Status Register
STAT1
Addr 05H
Bit RDRF OVRN PE FE RIE CTS1E TDRE TIE
Upon Reset
0
0
0
00
0
1
0
R/W
R
R
R
R R/W R/W R R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
/CTS1 Enable
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
Figure 37. ASCI Status Register (Ch. 1)
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DS971890301