W83877ATF Datasheet, PDF (93/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
4.3.1 ECP Register and Mode Definitions
NAME
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
ECP MODES
000-001
011
All
All
010
011
110
111
111
All
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE
000
001
010
011
100
101
110
111
DESCRIPTION
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
Note: The mode selection bits are bit 7-5 of the Extended Control Register.
4.3.2 Data and ecpAFifo Port
Modes 000 (SPP) and 001 (PS/2) (Data Port)
During a write operation, the Data Register latches the contents of the data bus on the rising edge of
the input. The contents of this register are output to the PD0-PD7 ports. During a read operation,
ports PD0-PD7 are read and output to the host. The bit definitions are as follows:
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Publication Release Date: April 1998
Version 0.51