W83877ATF Datasheet, PDF (148/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
FDCIDLSTS (Bit 2): FDC idle status.
0
FDC is now in the working state.
1
FDC is now in the sleeping state due to no FDC access, no IRQ, no DMA
acknowledge, and no enabling of the motor enable bits in the DOR register.
URAIDLSTS (Bit 1): UART A idle status.
0
UART A is now in the working state.
1
UART A is now in the sleeping state due to no UART A access, no IRQ, the
receiver is now waiting for a start bit, the transmitter shift register is now empty,
and no transition on MODEM control input lines.
URBIDLSTS (Bit 0): UART B idle status.
0
UART B is now in the working state.
1
UART B is now in the sleeping state due to no UART B access, no IRQ, the
receiver is now waiting for a start bit, the transmitter shift register is now empty,
and no transition on MODEM control input lines.
8.2.51 Configuration Register 41 (CR41), default=00H
When the device is in Extended Function mode and EFIR is 41H, the CR41 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
URBTRAPSTS
URATRAPSTS
FDCTRAPSTS
PRTTRAPSTS
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Devices' trap status.
These bits indicate that the individual device wakes up due to any I/O access, IRQ, and external input
to the device respectively. The device's idle timer reloads the initial count value from CR35-CR39,
depending on which device wakes up. These 4 bits are controlled by the printer port, FDC, UART A,
and UART B power down machines individually. The bits are set/cleared by W83877ATF
automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect.
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Publication Release Date: April 1998
Version 0.51