W83877ATF Datasheet, PDF (162/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

8.4.9 Power Management 1 Timer 1 (PM1TMR1)
Register Location:
<CR33>+8H System I/O Space
Default Value:
00h
Attribute:
Read only
Size:
8 bits
765
43
21
0
W83877ATF
TMR_VAL0
TMR_VAL1
TMR_VAL2
TMR_VAL3
TMR_VAL4
TMR_VAL5
TMR_VAL6
TMR_VAL7
Bit
Name
0-7 TMR_VAL
Description
This read-only field returns the running count of the power management timer.
This is a 24-bit counter that runs off of a 3.579545 MHZ clock, and counts
while in the system working state. The timer is reset and then continues
counting until the CLKIN input to the chip is stopped. If the clock is restarted
without a MR reset, then the counter will continue counting from where it
stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23)
goes from 0 to 1 or from 1 to 0. If the TMR_EN bit is set, the setting of the
TMR_STS bit will generate an SCI interrupt.
8.4.10 Power Management 1 Timer 2 (PM1TMR2)
Register Location:
<CR33>+9H System I/O Space
Default Value:
00h
Attribute:
Read only
Size:
8 bits
765
43
21
0
TMR_VAL8
TMR_VAL9
TMR_VAL10
TMR_VAL11
TMR_VAL12
TMR_VAL13
TMR_VAL14
TMR_VAL15
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Publication Release Date: April 1998
Version 0.51