W83877ATF Datasheet, PDF (109/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
8.2.3 Configuration Register 2 (CR2), default = 00H
When the device is in Extended Function mode and EFIR is 02H, the CR2 register can be accessed
through EFDR. This register is reserved.
8.2.4 Configuration Register 3 (CR3), default = 30H
When the device is in Extended Function mode and EFIR is 03H, the CR3 register can be accessed
through EFDR. The bit definitions are as follows:
7654321 0
Bit 7-bit 6: Reserved.
EPPVER (Bit 5):
This bit selects the EPP version of parallel port:
0
Selects the EPP 1.9 version
1
Selects the EPP 1.7 version (default)
Bit 4: Reserved.
Bit 3-bit 2: Reserved.
SUBMIDI
SUAMIDI
reserved
reserved
reserved
EPPVER
reserved
reserved
SUAMIDI (Bit 1):
This bit selects the clock divide rate of UARTA.
0
Disables MIDI support, UARTA clock = 24 MHz divided by 13 (default)
1
Enables MIDI support, UARTA clock = 24 MHz divided by 12
SUBMIDI (Bit 0):
This bit selects the clock divide rate of UARTB.
0
Disables MIDI support, UARTB clock = 24 MHz divided by 13 (default)
1
Dnables MIDI support, UARTB clock = 24 MHz divided by 12
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Publication Release Date: April 1998
Version 0.51