W83877ATF Datasheet, PDF (56/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
4.3.2.3 Set0.Reg2 - Interrupt Status Register/UART FIFO Control Register (ISR/UFR)
(1) Interrupt Status Register: (Write Only)
Mode
B7
B6
B5
B4
B3
B2
B1
B0
Legacy FIFO
FIFO
0
UART Enable Enable
0
IID2
IID1
IID0
IP
Advanced
UART
Reset Value
TMR_I
0
FSF_I TXTH_I DMA_I
0
1
0
HS_I
0
USR_I/ TXEMP_I RXTH_I
FEND_I
0
1
0
Legacy UART: Same as previous register defined.
Advanced UART:
Bit 7:
TMR_I - Timer Interrupt.
Bit 6:
Set to 1 when timer counts to 0. This bit will be affected by (1) the timer registers are
defined in Set4.Reg0 and Set4.Reg1, (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0)
should be set to 1, (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) should be
set to 1.
MIR, FIR modes:
FSF_I - Frame Status FIFO Interrupt.
Set to 1 when Frame Status FIFO is equal to or larger than the threshold level or Frame
Status FIFO time-out occurs. Clear to 0 when Frame Status FIFO is below the threshold
level.
Advanced UART/SIR/ASK-IR, Remote IR modes:
Not used.
Bit 5:
TXTH_I - Transmitter Threshold Interrupt.
Bit 4:
Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level. Clear
to 0 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level.
MIR, FIR, Remote IR modes:
DMA_I - DMA Interrupt.
Bit 3:
Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which
may be a Transmitter TC or a Receiver TC. Clear to 0 when this register is read.
HS_I - Handshake Status Interrupt.
Bit 2:
Set to 1 when the Handshake Status Register has a toggle. Clear to 0 when Handshake
Status Register (HSR) is read. Note that in all IR modes including SIR, ASK-IR, MIR,
FIR, and Remote Control, IR are defaulted to inactive except set IR Handshake Status
Enable (IRHS_EN) to 1.
Advanced UART/SIR/ASK-IR modes:
USR_I - UART Status Interrupt.
Set to 1 when overrun, or parity bit, or stop bit, or silent byte detected error in the UART
Status Register (USR) is set to 1. Clear to 0 when USR is read.
MIR, FIR modes:
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is
defined in the physical layer of IrDA version 1.1 (2) abort signal or illegal signal has been
detected during receiving valid data. Clear to 0 when this register is read.
Remote Controller mode:
- 52 -
Publication Release Date: April 1998
Version 0.51