W83877ATF Datasheet, PDF (146/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
8.2.47 Configuration Register (CR39), default=00H
When the device is in Extended Function mode and EFIR is 39H, the CR39 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
GSBCNT0
GSBCNT1
GSBCNT2
GSBCNT3
GSBCNT4
GSBCNT5
GSBCNT6
GSBCNT7
GSBCNT7 - GSBCNT0 (Bit 7 - bit 0): global stand-by idle timer count.
Once all devices of the chip (including UART A, UART B, FDC and the printer port) are all in the
power down state, the power down machine of W83877ATF chip loads this register value and counts
down. When the timer counts to zero, the whole chip enters the power down state, i.e., sleeping state.
If this register is set to 0, the power down function will be invalid. The time resolution of this register
value is minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). This register
is valid when the CHIPPME = 1 (CR32 bit 7), and (2) If the register is set to 00H, W83877ATF chip
will remain in the current state (working or sleeping).
8.2.48 Configuration Register 3A (CR3A), default=00H
When the device is in Extended Function mode and EFIR is 3AH, the CR3A register can be accessed
through EFDR. The bit definitions are as follows:
76543210
Bit 7 - bit 6 : Reserved, fixed at 0.
UPULLEN
reserved
SMI_EN
reserved
reserved
TMIN_SEL
reserved
reserved
TMIN_SEL (Bit 5): Time resolution of the auto power machines of all devices.
CR35 to CR39 store the initial counts of the devices.
0
one second
1
one miniute
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Publication Release Date: April 1998
Version 0.51