W83877ATF Datasheet, PDF (61/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 2:
MIR, FIR modes:
CRC_ERR - CRC Error
Set to 1 when an attached CRC is error.
Bit 1, 0:
OER - Overrun Error, RDR - RBR Data Ready
Definitions are same as for legacy UART.
4.3.2.7 Set0.Reg6 - Handshake Status Register (HSR)
Mode
B7
B6
B5
B4
B3
Legacy DCD
RI
DSR
CTS
TDCD
UART
Advanced DCD
RI
DSR
CTS
TDCD
UART
Reset Value
0
0
0
0
0
B2
FERI
FERI
0
B1
TDSR
TDSR
0
B0
TCTS
TCTS
0
Legacy/Advanced UART Register: These registers are defined the same as in the previous
description.
4.3.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Legacy
UART
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
FLC_ACT
Advanced
UART
Reset Value
0
UNDRN
0
RX_BSY/ LST_FE/
RX_IP RX_PD
0
0
S_FEND
0
Bit 2
Bit 2
0
0
Bit 1
Bit 1
Bit 0
Bit 0
LB_SF RX_TO
0
0
Legacy UART Register: These registers are defined the same as in the previous description.
Advanced UART Register:
Bit 7 MIR, FIR modes:
FLC_ACT - Flow Control Active
Set to 1 when flow control occurs. Clear to 0 when this register is read. Note that this will
be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR mode or
when MIR/FIR mode operated in DMA function switches to SIR mode.
Bit 6 MIR, FIR modes:
UNDRN - Underrun
Set to 1 when transmitter is empty and not set S_FEND (in this register bit 3) operated in
PIO mode or not TC (Terminal Count) operated in DMA mode. Clear to 0 when write to 1.
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Publication Release Date: April 1998
Version 0.51