W83877ATF Datasheet, PDF (68/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
4.3.5.3 Reg2 - Mapped UART FIFO Control Register (MP_UFR)
Read only. Reading this register returns UART FIFO Control Register (UFR) value of SET 0.
4.3.5.4 Reg3 - Sets Select Register (SSR)
Reading this register returns E4₁₆. Write it to select other register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2
default Value
1
1
1
0
0
1
Bit 1
SRR1
0
Bit 0
SRR0
0
4.3.6 Set4 - TX/RX/Timer counter registers and IR control registers.
Address Register Name
Offset
Register Description
0
TMRL
Timer Value Low Byte
1
TMRH Timer Value High Byte
2
IR_MSL Infrared mode Select
3
SSR
Sets Select Register
4
TFRLL Transmitter Frame Length Low Byte
5
TFRLH Transmitter Frame Length High Byte
6
RFRLL Receiver Frame Length Low Byte
7
RFRLH Receiver Frame Length High Byte
4.3.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)
This is a 12-bit timer with resolution of 1 ms, that is, the programmed maximum time is 2¹²-1 ms. The
timer is a down-counter. The timer starts down count when the bit EN_TMR (Enable Timer) of
Set4.Reg2. is set to 1. When the timer down counts to zero and EN_TMR=1, the TMR_I is set to 1.
When the counter down counts to zero, a new initial value will be re-loaded into timer counter.
4.3.6.2 Set4.Reg2 - Infrared mode Select (IR_MSL)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Advanced -
-
-
-
UART
Reset Value
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
IR_MSL1 IR_MSL0 TMR_TST EN_TMR
0
0
0
0
- 64 -
Publication Release Date: April 1998
Version 0.51