W83877ATF Datasheet, PDF (134/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
While in the Serial IRQ mode (IRQMODS=1, CR31 bit2), the above selection is invalid and all the
IRQ signal pins, from IRQ_A to IRQ_H, are in tri-state. The parallel port IRQ is dedicated to the
SERIRQ pin. For the host controller to correctly sample the parallel port IRQ, the parallel port IRQ
should be programmed to appear in one of IRQ/Data Frame sampling periods.
In Serial IRQ mode, the definition of PRTIQS3-PRTIQS0 (bit 3-bit 0) is as follows:
PRTIQS3-PRTIQS0 (Bit 3-bit 0): Select the IRQ/Data Frame sampling period on the SERIRQ pin.
CR27[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IRQ/Data Frame Period
None
IRQ1
Reserved for SMI
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
8.2.32 Configuration Register 28 (CR28)
When the device is in Extended Function mode and EFIR is 28, the CR28 register can be accessed
through EFDR. Default = 43H if CR6 bit 2 = 1; default = 00H if CR16 bit 2 = 0. The bit definitions are
as follows:
765
43
21
0
URBIQS0
URBIQS1
URBIQS2
URBIQS3
URAIQS0
URAIQS1
URAIQS2
URAIQS3
URAIQS3-URAIQS0 (Bit 7-bit 4): Allocate interrupt resource for UART A.
URBIQS3-URBIQS0 (Bit 3-bit 0): Allocate interrupt resource for UART B.
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Publication Release Date: April 1998
Version 0.51