W83877ATF Datasheet, PDF (64/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
4.3.4 Set2 - Interrupt Status or UART FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes.
Address Register Name
Offset
Register Description
0
ABLL
Advanced Baud Rate Divisor Latch (Low Byte)
1
ABHL
Advanced Baud Rate Divisor Latch (High Byte)
2
ADCR1 Advanced UART Control Register 1
3
SSR
Sets Select Register
4
ADCR2 Advanced UART Control Register 2
5
Reserved
-
6
TXFDTH Transmitter FIFO Depth
7
RXFDTH Receiver FIFO Depth
4.3.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
The two registers are the same as the legacy UART baud rate divisor latch in SET 1. Reg0~1. When
using advanced UART/SIR/ASK-IR mode operation, these registers should be programmed to set
baud rate. This is to prevent a backward operation occurring.
4.3.4.2 Reg2 - Advanced UART Control Register 1 (ADCR1)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Advanced BR_OUT
UART
Reset Value
0
-
EN_LOUT D_CHSW ALOOP
0
0
0
0
Bit 2
DMATHL
0
Bit 1
DMA_F
0
Bit 0
ADV_SL
0
Bit 7:
Bit 6:
Bit 5:
Bit 4:
BR_OUT - Baud Rate Clock Output
Write to 1 enables the programmed baud rate clock to output to DTR pin. This bit is the
only test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
Write to 1 enables output of transmitter data to IRTX pin during doing loopback
operation. Setting this bit can check output data with internal data.
D_CHSW - DMA TX/RX Channel Swap
If using signal DMA channel in MIR/FIR mode, then the DMA channel can be swapped.
D_CHSW
DMA Channel Selected
0
Receiver (Default)
1
Transmitter
Write to 1 enables output data during the ALOOP=1.
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Publication Release Date: April 1998
Version 0.51