W83877ATF Datasheet, PDF (9/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
1.0 PIN DESCRIPTION
Note: Refer to section 9.2 DC CHARACTERISTICS for details.
I/O8tc - TTL level output pin with 8 mA source-sink capability; CMOS level input voltage
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12ts - TTL level bi-directional pin with 12 mA source-sink capability and Schmitt-triggered input
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt - TTL level input pin
INts - TTL level Schmitt-triggered input pin
INcs - CMOS level Schmitt-triggered input pin
1.1 HOST INTERFACE
SYMBOL
D0−D7
A0−A10
IOCHRDY
MR
CS
A11
AEN
IOR
IOW
DACK_ A
PIN
66-73
51-55
57-61
75
5
6
2
62
63
64
41
I/O
I/O_24t
IN_t
OD₂₄
IN_ts
IN_ts
IN_ts
IN_t
IN_ts
IN_ts
IN_ts
FUNCTION
System data bus bits 0-7.
System address bus bits 0-10.
In EPP Mode, this pin is the I/O Channel Ready output to extend
the host read/write cycle.
Master Reset. Active high. MR is low during normal operations.
Active low chip select signal.
System address bus bit 11, when 16-bit address decoder is set to
logic 0 in which CR16.bit6 ( EN16SA ).
System address bus enable.
CPU I/O read signal.
CPU I/O write signal.
DMA acknowledge signal A.
DRQ_A
DRQ_B
DACK_ B
39 OUT_8t DMA request signal A.
100 OUT_12t DMA request signal B.
98
IN_ts DMA acknowledge signal B.
Publication Release Date: April 1998
-5-
Version 0.51