W83877ATF Datasheet, PDF (138/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 3 :ENBNKSEL - Bank select enable
= 0 Disable UART B bank selection
= 1 Enable UART B bank selection
Bit 2 :CLKINSEL - Clock input selection
= 0 The clock on pin CLKIN is 24 MHz
= 1 The clock on pin CLKIN is 48MHz
Bit 1, Bit 0: Reserved
8.2.37 Configuration Registers (CR2D)
When the device is in Extended Function mode and EFIR is 2D₁₆, the CR2D register can be
accessed through EFDR. This register default value is 00₁₆. The bit definitions are as follows:
765
43
21
0
DRTA0
DRTA1
DIS_PRECOMP0
DRTB0
DRTB1
DIS_PRECOMP1
Reserved
Reserved
This register controls the data rate selection for FDC. It also controls if precompensation is enabled.
DRTA1, DRTA0 (bit 1 - bit 0):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD A as follows:
Drive Rate Table
DRTA1
DRTA0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Data Rate
DRATE1
1
0
0
1
1
0
0
1
1
0
0
1
DRATE0
1
0
1
0
1
0
1
0
1
0
1
0
operational data rate
MFM
FM
1M
500K
300K
250K
1M
500K
500K
250K
1M
500K
2M
250K
---
250K
150K
125K
---
250K
250K
125K
---
250K
---
125K
- 134 -
Publication Release Date: April 1998
Version 0.51