W83877ATF Datasheet, PDF (143/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
8.2.41 Configuration Register 33 (CR33), default=00H
When the device is in Extended Function mode and EFIR is 33H, the CR33 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
reserved
reserved
PM1AD2
PM1AD3
PM1AD4
PM1AD5
PM1AD6
PM1AD7
PM1AD7 - PM1AD2 (Bit 7 - bit 2): Base address of the power management register block PM1.
This address is the base address of PM1a_EVT_BLK in the ACPI specification. The based address
should range from 01,0000,0000_b to 11,1111,0000_b ,i.e., 100H ~ 3F0H, where bit 1 and bit 0 of the
base address should be set to 0 and the based address is in the 16-byte alignment. Note that the
based address of PM1a_CNT_BLK is equal to PM1a_EVT_BLK + 4, and PM_TMR_BLK is equal to
PM1a_EVT_BLK + 8.
Bit 1 - bit 0: Reserved, fixed at 0.
8.2.42 Configuration Register 34 (CR34), default=00H
When the device is in Extended Function mode and EFIR is 34H, the CR34 register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
reserved
GPEAD1
GPEAD2
GPEAD3
GPEAD4
GPEAD5
GPEAD6
GPEAD7
GPEAD7 - GPEAD1 (Bit7 - bit 1): Base address of the power management register block GPE.
This address is the base address of GPE0_BLK in the ACPI specification. The base address should
range from 01,0000,0000b to 11,1111,1000b ,i.e., 100H ~ 3F8H, where bit 0 of the base address
should be set to 0 and the base address is in the 8-byte alignment. Note that the base address of
GPE1_BLK is GPE0_BLK + 4.
Bit 0: Reserved, fixed at 0.
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Publication Release Date: April 1998
Version 0.51