W83877ATF Datasheet, PDF (60/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 2: MIR, FIR modes:
EN_DMA - Enable DMA
Enable DMA function to transmit or receive. Before using this, the DMA channel should
be select. If RX DMA channel is set and TX DMA channel is disabled, then the single
DMA channel is used. In the single channel system, the bit of D_CHSW (DMA channel
swap, in Set 2.Reg2.Bit3) will determine RX DMA channel or TX DMA channel.
Other modes:
Not used.
Bit 1, 0: RTS, DTR
Functional definitions are the same as in legacy UART mode.
4.3.2.6 Set0.Reg5 - UART Status Register (USR)
Mode
B7
B6
B5
B4
B3
B2
Legacy
UART
RFEI
TSRE TBRE
SBD
NSER PBER
Advanced LB_INFR
UART
Reset Value
0
TSRE
0
TBRE MX_LEX PHY_ERR CRC_ERR
0
0
0
0
B1
OER
OER
0
B0
RDR
RDR
0
Legacy UART Register: These registers are defined the same as in the previous description.
Advanced UART Register:
Bit 7: MIR, FIR modes:
LB_INFR - Last Byte In Frame End
Set to 1 when the last byte of a frame is in the FIFO bottom. This bit indicates that one
frame is separated from another frame when RX FIFO has more than one frame.
Bit 6, 5: Same as legacy UART description.
Bit 4: MIR, FIR modes:
MX_LEX - Maximum Frame Length Exceed
Set to 1 when frame length from the receiver has exceeded the programmed frame
length, which is in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not receive
any data to RX FIFO.
Bit 3: MIR, FIR modes:
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received, where the illegal data symbol is defined
in physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will
be aborted, and a frame end signal is set to 1.
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Publication Release Date: April 1998
Version 0.51