W83877ATF Datasheet, PDF (107/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
8.2 Extended Function Index Registers (EFIRs), Extended Function Data Registers
(EFDRs)
After the extended function mode is entered, the Extended Function Index Register (EFIR) must be
loaded with an index value (0H, 1H, 2H, ..., or 29H) to access Configuration Register 0 (CR0),
Configuration Register 1 (CR1), Configuration Register 2 (CR2), and so forth through the Extended
Function Data Register (EFDR). The EFIRs are write-only registers with port address 251H or 3F0H
(as described in section 8.0) on PC/AT systems; the EFDRs are read/write registers with port address
252H or 3F1H (as described in section 8.0) on PC/AT systems. The function of each configuration
register is described below.
8.2.1 Configuration Register 0 (CR0), default = 00H
When the device is in Extended Function mode and EFIR is 0H, the CR0 register can be accessed
through EFDR. The bit definitions for CR0 are as follows:
7 6 54 3 2 1 0
IPD
reserved
PRTMODS0
PRTMODS1
reserved
reserved
reserved
reserved
Bit 7-bit 4: Reserved.
PRTMOD1 PRTMOD0 (Bit 3, 2):
These two bits and PRTMOD2 (CR9 bit 7) determine the parallel port mode of the W83877ATF (as
shown in the following Table 8-1).
Table 8-1
PRTMODS2
(BIT 7 OF CR9)
0
0
0
0
1
1
1
1
PRTMODS1
(BIT 3 OF CR0)
0
0
1
1
0
0
1
1
PRTMODS0
(BIT 2 OF CR0)
0
1
0
1
0
1
0
1
Normal
EXTFDC
Reserved
EXT2FDD
Reserved
EPP/SPP
ECP
ECP/EPP
- 103 -
Publication Release Date: April 1998
Version 0.51