W83877ATF Datasheet, PDF (139/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
DIS_PRECOMP0 (bit 2):
This bit controls if precompensation is enabled for FDD A.
0 enable precompensation for FDD A
1 disable precompensation for FDD A
DRTB1, DRTB0 (bit 4 - bit 3):
These two bits combining with data rate selection bits in Date Rate Register select the operational
data rate for FDD B as shown in last table.
DIS_PRECOMP1 (bit 5):
This bit controls if precompensation is enabled for FDD B.
0 enable precompensation for FDD B
1 disable precompensation for FDD B
Bit 7 - bit 6: Rreserved.
8.2.38 Configuration Register 2E (CR2E), default = 2eH
When the device is in Extended Function mode and EFIR is 2eH, the CR2E register can be accessed
through EFDR. The bit definitions are as follows:
765
43
21
0
nEN16SA
ENPNF
INVRD
EN24X2M
DIS_BST
Reserved
Reserved
Reserved
ENPNF (Bit 0):
0
Disable Printer Not Floppy function. (Default)
1
Enable Printer Not Floopy function.
nEN16SA (Bit 1):
0
Enable 16-bit address decoder in the ISA bus. If the function of full ISA address
decoder is used, the device of COM B will be Changed to SIR/FIR function
automatically.
1
Disable 16-bit address decoder in the ISA bus.
INVRD (Bit 2):
0
Disable inverting RDATA from floppy disk input signal. (Default)
1
Enable inverting RDATA from floppy disk input signal.
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Publication Release Date: April 1998
Version 0.51