W83877ATF Datasheet, PDF (65/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit 3:
Bit 2:
ALOOP - All mode Loopback
Write to 1 enables loopback in all modes.
DMATHL - DMA Threshold Level
Sets DMA threshold level as shown in the table below.
DMATHL
0
1
TX FIFO Threshold
16-Byte
32-Byte
13
13
23
7
RX FIFO Threshold
(16/32-Byte)
4
10
Bit 1:
Bit 0:
DMA_F - DMA Fairness
DMA_F
Function Description
0
DMA request (DREQ) is forced inactive after 10.5us
1
No effect on DMA request.
ADV_SL - Advanced mode Select
Write to 1 selects advanced mode.
4.3.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E016. Write it to select other register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SSR
default Value
SSR7
1
SSR6
1
SSR5
1
SSR4
0
SSR3
0
SSR2
0
Bit 1
SRR1
0
Bit 0
SRR0
0
4.3.4.4 Reg4 - Advanced UART Control Register 2 (ADCR2)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced DIS_BAC
-
PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
UART
K
Reset Value
0
0
0
0
0
0
0
0
Bit 7:
Bit 6:
DIS_BACK - Disable Backward Operation
Write to 1, read or write BLL or BHL (Baud rate Divisor Latch Register, in Set1.Reg0~1),
will disable backward legacy UART mode. When using legacy SIR/ASK-IR mode, this bit
should be set to 1 to avoid backward operation.
Reserved, write 0.
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Publication Release Date: April 1998
Version 0.51