W83877ATF Datasheet, PDF (72/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
4.3.7.4 Set5.Reg4 - Infrared Config Register 1 (IRCFG1)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IRCFG1
-
FSF_TH FEND_M AUX_RX
-
Reset Value
0
0
0
0
0
Bit 2
-
0
Bit 1
Bit 0
IRHSSL IR_FULL
0
0
Bit 7:
Bit 6:
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the
FSF_I. The threshold level values are defined as follows.
FSF_TH
0
1
Status FIFO Threshold Level
2
4
Bit 5:
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
FEND_MD - Frame End mode
Write to 1 enables hardware automatically to split same length frame defined Set4.Reg4
and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
Write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved, write 0.
IRHSSL - Infrared Handshake Status Select
Write to 0 brings the HSR (Handshake Status Register) into normal operation the same
as UART. Write to 1 disables HSR; reading HSR will then return 3016.
IR_FULL - Infrared Full Duplex Operation
Write to 0 will cause IR function to operate in half duplex. Write to 1 will cause IR
function to operate in full duplex.
4.3.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO)
This register are indicated the FIFO bottom of frame status.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
FS_FO FSFDR LST_FR
-
MX_LEX PHY_ERR CRC_ERR RX_OV
Reset Value
0
0
0
0
0
0
0
Bit 0
FSF_OV
0
- 68 -
Publication Release Date: April 1998
Version 0.51