W83877ATF Datasheet, PDF (159/191 Pages) Winbond – enhanced version from Winbonds most popular I/O chip W83877F

W83877ATF
Bit
Name
0
TMR_EN
1-4 Reserved
5
GBL_EN
6-7 Reserved
Description
This is the timer carry interrupt enable bit. When this bit is set, an SCI event is
generated anytime the TMR_STS bit is set. When this bit is reset no interrupt
is generated when the TMR_STS bit is set.
Reserved. These bits always return a value of zero.
The global enable bit. When both the GBL_EN bit and the GBL_STS bit are
set, an SCI interrupt is raised.
Reserved.
8.4.4 Power Management 1 Enable Register 2 (PM1EN2)
Register Location:
<CR33>+3H System I/O Space
Default Value:
00h
Attribute:
Read/write
Size:
8 bits
765
43
21
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit Name
Description
0-7 Reserved Reserved. These bits always return a value of zero.
8.4.5 Power Management 1 Control Register 1 (PM1CTL1)
Register Location:
<CR33>+4H System I/O Space
Default Value:
00h
Attribute:
Read/write
Size:
8 bits
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Publication Release Date: April 1998
Version 0.51